• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.3
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• pp.362-367
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• 2010

In this paper, we describe implementation of FPGA-based Nios II embedded processor system and linux device driver for image monitoring system which is supplement weakness for fixed surveillance area of existing CCTV system and by manual operation of the camera's moving. Altera Nios II processor 8.0 is supported MMU which is stable and efficient managed memory. We designed the image monitoring and control system by using Altera Nios II soft-core processor system which is flexible in various application and excellent adaptability. By implementation of camera device driver and VGA decvice driver for Linux-based Nios II system, we implemented image serveillance system for Nios II embedded processor system.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.2
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• pp.83-90
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• 2012

In this paper, an intelligent visual surveillance system based on a NIOS II embedded platform is implemented. By this time, embedded based visual surveillance systems were restricted for a special purpose because of high dependence upon hardware. In order to improve the restriction, we implement a flexible embedded platform, which is available for various purpose of applications. For high speed processing of software based programming, we improved performance of the system which is integrated the SOPC type of NIOS II embedded processor and image processing algorithms by using software programming and C2H(The Altera NIOS II C-To-Hardware(C2H) Acceleration Compiler) compiler in the core of the hardware platform. Then, we constructed a server system which globally manage some devices by the NIOS II embedded processor platform, and included the control function on networks to increase efficiency for user. We tested and evaluated our system at the designated region for visual surveillance.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.4
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• pp.580-585
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• 2010

In this paper, The object Tracking System is designed by SOPC based Nios II embedded processor and C2H compiler. And this system using single PTZ camera can effectively control IPs in the platform of SOPC based Nios II Embedded Processor and creating IP by C2H(C-To-Hardware) compiler for image-in/output, image-processing and devices of communication that can supply various monitoring information to network or serial. Accordingly, Special quality and processing speed of object tracking using high-quality algorism in the system is improved by hardware/software programming methods.

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.245-255
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• 2009

Recently, embedded processor systems have been widely used in the field of information communication devices and increased its use range and influence. The embedded systems are offered variety of functions, and its operating systems have been developed to make them easy to repair and maintain. Especially embedded linux is very cheap and provide a lot of equipment drivers. Also we can set up our own system because the source code is opened. In this paper, we describe the implementation of Touch panel and TFT-LCD device driver that are widely used for multimedia application. We designed the system hardware by using Altera Nios II embedded system. And we implemented the device drivers of frame buffer, touch panel and i2s based on uClinux for multimedia application, and tested actual operations of the integrated system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.366-373
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• 2007

In this paper we propose a multi-channel speech pickup system for calling quality enhancement of hands-free communication using ALTERA Nios-II processor. Multi-channel speech pickup system uses Delay-and-Sum beamformer with zero-padding interpolator. This paper implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. The proposes speech pickup embedded system shows a good agreement with those of computer simulation(MATLAB) and conventional DSP processor(TMS320C6711) result. The proposed method is effective more than previous methods in cost and design processing time. As a result, LE(Logic Element) of hardware used 3,649/5,980(61%) on a chip.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.1
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• pp.13-19
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• 2011

In this paper, a visual surveillance system using SOPC based NIOS II embedded processor and C2H compiler was implemented. In this system, the IP is constructed by C2H compiler for the output of the camera images, image processing, serial communication and network communication, then, it is implemented to effectively control each IP based on the SOPC and the NIOS II embedded processor. And, an algorithm which updates the background images for high speed and robust detection of the moving objects is proposed using the Adaptive Gaussian Mixture Model(AGMM). In results, it can detecte the moving objects(pedestrians and vehicles) under day-time and night-time. It is confirmed that the proposed AGMM algorithm has better performance than the Adaptive Threshold Method(ATM) and the Gaussian Mixture Model(GMM) from our experiments.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.639-645
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• 2015

Checksum and residue checking accelerators were implemented on a Nios II core-based platform according to component method, in which the corresponding hardware was implemented with HDL coding, a custom instruction method, in which the instruction set of the processor was extended, and the C2H method, in which the corresponding logic was automatically created by the C2H compiler. The processing results from each accelerator for each algorithm were then examined and compared. The results of the comparison showed that the accelerator implemented with the C2H method is the fastest in terms of the execution time, and the accelerator with custom instruction requires the least add-on from the viewpoint of add-on hardware.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06d
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• pp.327-331
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• 2008

본 논문에서는 ALtera Cyclone II FPGA와 VGA Controller, ISP1362 Host Controller, DM9000A Ethernet Controller를 사용하여 FPGA를 구성하고, ${\mu}Clinux$를 포팅하여 Nano-X 기반에서 JPEG 파일을 디스플레이 시키는 임베디드 디지털 액자를 구현한다. 구현한 시스템은 일반적인 마이크로프로세서를 사용하지 않고 Altera 사의 Cyclone II FPGA를 이용해 직접 프로세서를 설계하고, ISP1362 Host Controller를 이용하여 USB 드라이브를 인식하며, DM9000A를 통해 웹과 연결하여 웹서버로부터 전송되어진 JPEG 이미지를 Display 할 수 있도록 설계하였다.