• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05a
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• pp.55-58
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• 2003

FeMn based spin valves often consist of a NiFe/FeMn/NiFe trilayer structure. We have investigated the evolution of exchange bias at the bottom and top interfaces in the NiFe(5nm)/FeMn(x)/NiFe(5nm) trilayer structure as a function of FeMn thickness in the range 3 nm to 30 nm. The XRD results indicate (111) textured growth for NiFe and FeMn layers. The magnetization studies using VSM show two hysteresis loops corresponding to the bottom NiFe seed layer and top NiFe layers with greater bias for the bottom NiFe layer, for FeMn thickness equal to and above 5 nm. The larger exchange bias for the bottom seed layer is confirmed by the surface sensitive MOKE hysteresis loop measurements which show gradual weakening of the MOKE hysteresis loop for the bottom NiFe layer with increasing FeMn thickness. The observed large exchange bias in a spin valve structure is usually attributed to the pinning NiFe layer on top of the FeMn layer, even when a NiFe seed layer of a few nm thickness is present, whereas, in reality it may be arising from the bottom seed layer, as shown by the present study.

• Journal of Radiation Industry
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• v.8 no.3
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• pp.141-146
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• 2014

Nickel (Ni) electroplating was implemented by using a metal Ni powder in order to establish a $^{63}Ni$ plating condition on the PN junction semiconductor needed for production of beta-voltaic battery. PN junction semiconductors with a Ni seed layer of 500 and $1000{\AA}$ were coated with Ni at current density from 10 to $50mA\;cm^{-2}$. The surface roughness and average grain size of Ni deposits were investigated by XRD and SEM techniques. The roughness of Ni deposit was increased as the current density was increased, and decreased as the thickness of Ni seed layer was increased. The results showed that the optimum surface shape was obtained at a current density of $10mA\;cm^{-2}$ in seed layer with thickness of $500{\AA}$, $20mA\;cm^{-2}$ of $1000{\AA}$. Also, pure Ni deposit was well coated on a PN junction semiconductor without any oxide forms. Using the line width of (111) in XRD peak, the average grain size of the Ni thick firm was measured. The results showed that the average grain size was increased as the thickness of seed layer was increased.

• 한국금형공학회:학술대회논문집
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• 2008.06a
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• pp.35-38
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• 2008

A pattern master and a Ni stamper for 50nm class of patterns are fabricated through e-beam lithography and Ni electroforming process. A model pattern set is designed, which is based on unit patterns of 50nm, 100nm, 150nm and 200nm in length and 50nm in width. The e-beam process is optimized to fabricate designed patterns with some parameters including dose, accelerating voltage, focal distance and developing time. For Ni electroforming to fabricate Ni stamper, a seed layer, a conducting layer, is deposited first on the pattern master fabricated by an e-beam lithography process. Ni, Ti/Ni and Cr are first tested to find optimal seed layer process. Currently the best result is obtained when adopting Cr deposited to be 100nm thick with continuous tilting motion of the master substrate during the deposition process.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.63-67
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• 2014

As the demand for fine-pitch FPCB (Flexible Printed Circuit Board) increases, so do the number of applications of sputtered FCCL (Flexible Copper Clad Laminate). Furthermore, as the width between the circuit patterns decreases, greater defects are observed in the migration phenomenon. In this study we observed changes in ion migration in real circuit-pattern width using sputtered FCCL. We found that as the applied voltage and residue thickness of the NiCr seeds increase, ion migration occurs faster. If the NiCr seed layer thickens due to a high cathode power and long deposition time while being sputtered, the NiCr will form a residue that quickly becomes a factor for incurring ion migration.

• Korean Journal of Metals and Materials
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• v.48 no.12
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• pp.1116-1122
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• 2010

Metal interconnections of multilayer Al/Ni and TiW/seed-Ni/Ni were formed on glass, and the adhesion strength and nanoindentation response of the composite layers were evaluated. The Al/Ni multilayer was formed by an anodic bonding of glass to Al and subsequent electroless plating of Ni, while the TiW/Ni multilayer was fabricated by sputter deposition of TiW and seed-Ni onto glass and electroless plating of Ni. Because of the diffusion of aluminum into glass during the anodic bonding, anodically bonded glass/Al joint exhibited greater interfacial strength than the sputtered glass/TiW one. The Al/Ni on glass also showed excellent resistance against delamination by bending deformation compared to the TiW/seed-Ni/Ni on glass. From the nanoindentation experiment of each metal layer on glass, it was found that the aluminum layer had extremely low hardness and elastic modulus similar to the glass substrate and played a beneficial role in the delamination resistance by lessening stress intensification at the joint. The indentation data of the multilayers also supported superior joint reliability of the Al/Ni to glass compared to that of the TiW/seed-Ni/Ni to glass.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.212-212
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• 2003

Many of the spin valve multilayer structures with FeMn as antiferromagnetic layer consist of a NiFe/FeMn/NiFe trilayer where the bottom NiFe layer is the seed layer to facilitate the growth of (111) gama-FeMn antiferromagnetic phase and the top NiFe layer forms the pinned layer[1], In this study, exchange bias of bottom NiFe layer has been investigated as functions of thicknesses of top and bottom NiFe in NiFe/FeMn/NiFe, prepared by rf magnetron sputtering, MH-loop was measured by vibration sample magnetometer (VSM). Two hysteresis loops are corresponded to bottom and top layers, similar to reported loops in spin valve structure. Exchange bias of bottom NiFe could be induced by the interfacial coupling between bottom NiFe and FeMn. But those coupling are strongly dependent on the top and bottom NiFe thicknesses, revealing anomalous character ul exchange bias of bottom NiFe layer.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.75-75
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• 2009

연성회로기판은 일반적으로 절연체를 이루는 폴리이미드와 전도체를 이루는 구리로 구성되어 있다. 폴리이미드는 뛰어난 열적 화학적 안정성, 기계적 특성, 공정성 등의 장점으로 인해 연성회로기판의 절연체로서 제안되었지만 전도체를 이루는 구리와의 접합 특성이 우수하지 않기 때문에 많은 연구가 현재까지 진행되고 있고, 그 결과 연성회로기판의 접합 특성에 많은 개선이 이루어짐과 동시에 다양한 공정 방법이 제안되고 있다. 하지만 고온다습한 환경에서 사용될 경우 폴리이미드의 높은 흡습성과, 구리와 seed layer의 산화 문제로 인해 접합 특성이 저하된다는 단점 또한 가지고 있다. 따라서 본 연구를 통해 고온다습한 조건하에서 seed layer가 80Ni/20Cr 합금으로 구성된 연성회로기판의 seed layer의 두께와 시효시간으로 인해 발생하는 접합 신뢰성의 차이를 관찰하였다. 본 연구에서는 두께 $25{\mu}m$의 폴리이미드 위에 각각 100, 200, $300{\AA}$ 두께의 80Ni/20Cr의 합금 조성을 가지는 seed layer를 스퍼터링 공정을 통해 형성한 후 전해도금법을 이용하여 $8{\mu}m$ 두께의 구리 전도층을 형성하였다. 접합 특성 평가를 위해 ICP 규격에 따라 전도층 패턴을 폭 3.2mm, 길이 230mm로 시편을 제작하여 50.8mm/min의 이송 속도로 각 시편당 8회의 $90^{\circ}$ peel test를 실시하였다. 또한 $85^{\circ}C$/85% 항온항습 조건하에서 각각 24, 72, 120, 168시간 동안 시효 처리 후 같은 방법으로 연성회로기판의 접합 특성을 평가하였다. 파면의 형상과 조성을 분석하기 위해 SEM (Scanning electron microscope)과 EDS (Energy-dispersive X-ray spectroscopy)를 사용하였으며, 파면의 조도 측정을 위해 AFM (Atomic force microscope)을 사용하였다. 또한 파면의 잔여물 분석을 위해 EPMA (Energy probe microanalysis)를 사용하였고 계면의 화학적 결합상태를 분석하기 위해 XPS (X-ray photoelectron spectroscopy)를 통해 파면을 분석하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.84-87
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• 2003

Since Pb-free solder alloys have been used extensively in microelectronic packaging industry, the interaction between UBM (Under Bump Metallurgy) and solder is a critical issue because IMC (Intermetallic Compound) at the interface is critical for the adhesion of mechanical and the electrical contact for flip chip bonding. IMC growth must be fast during the reflow process to form stable IMC. Too fast IMC growth, however, is undesirable because it causes the dewetting of UBM and the unstable mechanical stability of thick IMC. UP to now. Ni and Cu are the most popular UBMs because electroplating is lower cost process than thin film deposition in vacuum for Al/Ni(V)/Cu or phased Cr-Cu. The consumption rate and the growth rate of IMC on Ni are lower than those of Cu. In contrast, the wetting of solder bumps on Cu is better than Ni. In addition, the residual stress of Cu is lower than that of Ni. Therefore, the alloy of Cu and Ni could be used as optimum UBM with both advantages of Ni and Cu. In this paper, the interfacial reactions of Sn-3.5Ag-0.7Cu solder on Ni-xCu alloy UBMs were investigated. The UBMs of Ni-Cu alloy were made on Si wafer. Thin Cr film and Cu film were used as adhesion layer and electroplating seed layer, respectively. And then, the solderable layer, Ni-Cu alloy, was deposited on the seed layer by electroplating. The UBM consumption rate and intermetallic growth on Ni-Cu alloy were studied as a function of time and Cu contents. And the IMCs between solder and UBM were analyzed with SEM, EDS, and TEM.

• Korean Journal of Materials Research
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• v.24 no.9
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• pp.443-450
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• 2014

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

• Journal of the Korean Magnetics Society
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• v.13 no.3
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• pp.91-96
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• 2003

Cross-geometrical Cr/Co/Al-Ox/Co/Ni-Fe tunnel junctions were fabricated by magnetron sputtering. To form an insulating layer, The Al layer was oxidized in an atmosphere of oxygen-argon mixture at low power after deposition. To enhance the coercivity of the bottom Co layer, The Cr seed layer was deposited on the glass and it led to increase in coercivity. The coercivity increase is due to the increase of roughness through the Cr thickness. In over oxidation time, the oxidation of Co bottom layer and flat interface of insulator can increase the bottom Co coercivity. But TMR ratio gradually decrease. TMR ratio is relevant with Cr thickness, insulator thickness, and oxidation time. The maximum TMR ratio was 14% at room temperature and the TMR ratio was decreased to half at 0.51 V.