• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.487-488
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• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.489-490
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• 2016

본 논문에서는 인버터 시스템의 가격을 줄이기 위해 3-레벨 NPC 인버터의 중성단에 하나의 션트 저항을 삽입함으로써 AC 전동기의 3상 전류를 획득하는 방법을 제안한다. 션트 저항으로부터 정확한 상 전류를 획득하기 위해서는 최소한의 시간이 필요하며 때문에 측정불가영역이 존재하게 된다. 기존의 측정불가영역으로 부터 상 전류를 복원하는 방법은 스위칭 패턴을 이동시키거나 공간 벡터 전압 변조 기법(SVPWM) 이외의 변조 기법을 이용하였는데 이러한 방법은 전류에 고조파를 증가시켜 효율을 떨어뜨리고 소음을 발생시킨다. 본 논문에서는 동기 좌표계 d-q축 비례적분제어기와 전동기 시스템의 전달함수를 이용하여 지령 전류로부터 실제 전류와 같은 전류를 얻는 방법을 통해 기존의 문제점들을 개선하는 방법을 제안한다. 제안된 방법은 시뮬레이션을 통해 증명하였다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• Journal of IKEEE
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• v.24 no.3
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• pp.867-876
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• 2020

This paper proposes a neutral-point voltage ripple reduction of high frequency injection sensorless control of IPMSM fed by a three-level inverter. The high frequency voltage injection method has been successfully applied to sensorless control for IPMSM at low speed region. In the process of high frequency voltage injection sensorless control for IPMSM, the neutral-point voltage ripple is increased. It should be reduced because it distorts the output current and decreases a life time of DC-link capacitor. The proposed method in this paper reduces the neutral-point voltage ripple by compensating the reference voltage, and the compensation value is calculated simply with reference voltages and currents. The effectiveness of the proposed method is verified by simulation results.

• Journal of Power Electronics
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• v.18 no.3
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• pp.702-713
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• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1306-1315
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• 2016

Modern power systems driven by high-power converters have become inevitable in view of the ever increasing demand for electric power. The total power loss can be reduced by limiting the switching losses in such power converters; increased power efficiency can thus be achieved. A reduced switching frequency that is less than a few hundreds of hertz is applied to power converters that produce output waveforms with high distortion. Selective harmonic elimination pulse width modulation (SHEPWM) is an optimized low switching frequency pulse width modulation method that is based on offline estimation. This method can pre-program the harmonic profile of the output waveform over a range of modulation indices to eliminate low-order harmonics. In this paper, a SHEPWM scheme for three-phase three-leg neutral point clamped inverter is proposed. Aside from eliminating the selected harmonics, the DC capacitor voltages at the DC bus are also balanced because of the symmetrical pulse pattern over a quarter cycle of the period. The technique utilized in the estimation of switching angles involves the firefly algorithm (FA). Compared with other techniques, FA is more robust and entails less computation time. Simulation in the MATLAB/SIMULINK environment and experimental verification in the very large scale integration platform with Spartan 6A DSP are performed to prove the validity of the proposed technique.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.505-512
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• 2007

The object of this paper is to study a new control structure for sensorless induction machines dedicated to electrical drives using a three-level voltage source inverter VSI-NPC. The amplitude and the rotating speed of the flux vector can be controlled freely. The scheme investigated is an Enhanced direct torque control "EDTC" for electric vehicle propulsion. The considered application imposes some constraints which are achieved in EDTC control (fast torque response, optimal switching logic, torque control at zero speed, and large speed control. The results obtained for an induction motor indicate superior performance over the FOC type without need for any mechanical sensor.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.173-183
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• 2014

In this paper, an analysis of power losses for the three-level T-type and neutral-point clamped (NPC) PWM inverters is presented, in which the conduction and switching losses of semiconductor devices of the inverters are taken into account. In the inverter operation, the conduction loss depends on the modulation index (MI) and power factor (PF), whereas the switching loss depends on the switching frequency. Power losses for the T-type and NPC inverters are analyzed and calculated at the different operating points of MI, PF and the switching frequency, in which the four different models of semiconductor devices are adopted. In the case of lower MI, the NPC-type is more efficient than the T-type, and vice versa. The validity of the power loss analysis has been verified by the simulation results.