• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• Journal of Sensor Science and Technology
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• v.15 no.2
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• Journal of Sensor Science and Technology
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• v.12 no.2
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• pp.57-65
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• 2003

When a vision chip for edge detection using CMOS process is designed, there is a necessity to implement local light adaptive-function for detecting distinctive features of an image at a wide range of light intensities. Local light adaptation is to achive the almost same output level by changing the size of receptive-fields of the local horizontal cell layers according to input light intensities, based on the lateral inhibitive-function of the horizontal cell. Thus, the almost same output level can be obtained whether input light intensities are much or less larger than background. In this paper, the horizontal cells using a resistive network which consists of p-MOSFETs were modeled and analyzed, and the local light adaptive-mechanism of the designed vision chip using the resistive network was verified.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2140-2142
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• 2003

Recently, TCP/IP on Ethernet protocol is in use environment of LAN have developed a single chip by hardware. Therefore, the study about the single chip applies to the system control application like information electronic appliances, manufacturing automation machine has been made progress. This paper is the development of experimental Client node and Serve node that can transfer input-output data needed on Network Control System Client node is a sensor part of control system, that is, an analog signal is applicable to output data convert AD through LAN. Server node data sended in client convert DA, and then it is applicable to driver of Control System, so it achieves its part. In this study, is prove that using TCP/IP construct Network Control System.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.2
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• pp.97-104
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• 2011

This paper deals with the quick and precise disaster prevention automation system (DPAS) based on information communication technology (IT) that detects fire and disasters in the building automatically and quickly and then activates the facilities to extinguish fire and disasters, monitoring such situation in a real time through wire-wireless communication network. The proposed DPAS is applied a programmable logic controller (PLC) of one-chip type which is smallsize and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLC analyzes detected signals from sensors in a case of fire and disasters, then activates fire extinguishing facilities for rapid suppression. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication. The transferred data sounds an emergency alarm signal, and operates a monitoring program. The proposed DPAS based on IT will minimize the life and wealth loss from rapid measures while prevents fire and disasters.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.3
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• pp.120-132
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• 2008

Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energy-efficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoC-based systems, including network topology, task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1654-1660
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• 2004

In this paper, we describes the design and implementation of LonWorks communication module for distributed intelligent control using LonWorks technology of Echelon. LonWorks communication module can be divided hardware and firmware. First, hardwares is divided into microcontroller attaching sensors and LonWorks components for working together control network and data network. Hardwares are consisted of neuron chip, microcontroller, transceiver, LONCard. Second, operating firmware is realized with neuron C using NodeBulider 3.0 development tool. Produced and implemented LonWorks communication module is pretested using LTM-10A, Gizmo 4 I/O board, parallel I/O Interface. For field test, microcontroller module part is tested by HyperTerminal, communication procedure in data network is certified by transmitting and receiving short message using LonMaker for Windows tool. Herewith, LON technology is based on network communication technique using LonWorks.