• Journal of KIISE:Databases
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• v.29 no.6
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• pp.492-501
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• 2002

An asynchronous trigger processor (ATP) is a oftware system that processes triggers after update transactions to databases are complete. In an ATP, discrimination networks are used to check the trigger conditions efficiently. Discrimination networks store their internal states in memory nodes. TriggerMan is an ATP and uses Gator network as the .discrimination network. The changes in databases are delivered to TriggerMan in the form of tokens. Processing tokens against a Gator network updates the memory nodes of the network and checks the condition of a trigger for which the network is built. Parallel token processing is one of the methods that can improve the system performance. However, uncontrolled parallel processing breaks trigger processing semantic consistency. In this paper, we propose four trigger processing consistency levels that allow parallel token processing with minimal anomalies. For each consistency level, a parallel token processing technique is developed. The techniques are proven to be valid and are also applicable to materialized view maintenance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.751-755
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• 1997

This paper presents a new scheme of neural network controller to improve to improve the robustuous of robot manipulator using digital signal processors. Digital processors, DSPs, are micro-processors that are particularly developed for fast numerical computations involving sums and products of variables. Digital version of most advanced control algorithms can be defined as sums and producrs of measured variables, thus it can be programmed and executed through DSPs. In addition, DSPs are as fist in computation as most 32-bit micro-processors and yet at a fraction of their prices. These features make DSPs a viable computational tool in digital implementation of sophisticated controllers. During past decade it was proposed the well-established theorys for the adaptive control of linear systems, but there exits relativly little gensral theoral for the adaptive control of nonlinear systems. Perforating of the proposed controller is illustrated. This paper describes a new approach to the design of adaptive controller and implementation of real-time control for assembling robotic manipulator using digital signal processor. Digital signal processors used in implementing real time adaptive control algorithm are TMS320C50 series made in TI'Co..

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1560-1565
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• 2007

A surveillance system is used many industrial places, and public places to monitor the present situation. Most of the existing surveillance system is composed of the monitors and a lot of cameras that are installed each place to be monitored. The system is usually using the CCTV, closed circuit television, system that is a passive surveillance system. Urban transit operation corporations use the passive surveillance system to monitor the situation of the passengers, and the status of the important facilities. However the officers or operators cannot monitor all of the situation or status constantly, and cannot respond to emergency. In this paper, we propose a sensor network-based intelligent surveillance system to solve these problems. The proposed system is composed of a lot of intelligent sensors that can determine the present status and integrated processor units to detect more precisely events using the information from the sensors. The sensors and the integrated processor are connected by communication network. The proposed system can be installed and used without a lot of change of the existing facilities such as the enormous communication bandwidth increase.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.50-57
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• 2004

Two processors are generally used to drive the power circuits for controlling the dual motors independently. In this paper, we propose the new control scheme to drive dual inverters using only one controller with the aid of CAN network. The proposed system is very useful compared to conventional techniques especially in case of controlling the combined dual motors because the control algorithm can be implemented by the software program only without any additional processor or hardware interfacing. The proposed system is implemented and verified experimentally.

• Journal of Information Processing Systems
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• v.14 no.1
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• pp.270-279
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• 2018

PCI Express (PCIe) bus, which was only used as an internal I/O bus of a computer system, has expanded its function to outside of a system, with progress of PCIe switching processor. In particular, advanced features of PCIe switching processor enable PCIe bus to serve as an interconnection network as well as connecting external devices. As PCIe switching processors more advanced, it is required to consider the different adapter card architecture. This study developed multipurpose adapter cards by applying an on-board optical module, a latest optical communications element, in order to improve transfer distance and utilization. The performance evaluation confirmed that the new adapter cards with long cable can provide the same bandwidth as that of the existing adapter cards with short copper cable.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.63-73
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• 2004

This paper proposes an efficient centralized sin91e buffer management algorithm to arbitrate access contention mon processors on the multi-processor system for high-speed Packet filtering and proves that the algorithm provides reasonable performance by implementing it and applying it to a real multi-processor system. The multi-processor system for parallel packet filtering is modeled based on a network processor to distribute the packet filtering rules throughout the processors to speed up the filtering. In this paper we changed the number of processors and the processing time of the filtering rules as variables and measured the packet transfer rates to investigate the performance of the proposed algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.972-982
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• 1988

In multiprocessor systems, there are Omega network and M network among various MIN's which interconnect the processor and memory modules. Both one-path Omega network and two-path M network are composed of Log2N stages. In this paper, Augmented M network (AMN) with 2**k+1 paths and Augmented Omega network (AON) with 2**k paths are proposed. The proposed networks can be acomplished by adding K stage(s) to M network and Omega network. Using destination tag, routing algorithm for AMN and AON becomes simple and multiple faults are tolerant. By evaluating RST(request service time) performance of AMN and AON with (Log2N)+K stages, we demonstrated the fact that MMIN (AMN) with 2**k+1 paths performs better than MMIN(AON) with 2**k+1. paths.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.12
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• pp.804-810
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• 2004

There are two important things for the general purpose neural network processor. The first is a capability to build various structures of neural network, and the second is to be able to support suitable learning method for that neural network. Some way to process various learning algorithms is required for on-chip learning, because the more neural network types are to be handled, the more learning methods need to be built into. In this paper, an improved hardware structure is proposed to compute various kinds of learning algorithms flexibly. The hardware structure is based on the existing modular neural network structure. It doesn't need to add a new circuit or a new program for the learning process. It is shown that rearrangements of the existing processing elements can produce several neural network learning modules. The performance and utilization of this module are analyzed by comparing with other neural network chips.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.5
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• pp.433-438
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• 2012

In this paper, a operation network system equipped with onboard wireless communication systems and ground-based mission control systems is proposed for swarm flight of small UAVs. This operating system can be divided into two networks, UAV communication network and ground control system. The UAV communication network is intend to exchange the informations of navigation, mission and flight status with minimum time delay. The ground control system consisted of mission control systems and UDP network. Proposed operation network system can make a swarm flight of various UAVs, execute complex missions decentralizing mission to several UAVs and cooperte several missions. Finally, PILS environments are developed based on the total operating system.