• Title/Summary/Keyword: Network processor

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The VLAN implementation scheme on IBM-NP4GS3 based Packet Forwarding Engine (IBM NP4GS3 기반 패킷 포워딩 엔진에서의 VLAN 구현 방안)

  • 최창식;곽동용
    • Proceedings of the Korean Information Science Society Conference
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    • 2002.10e
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    • pp.502-504
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    • 2002
  • 기존 라우터시스템에서의 패킷 포워딩 엔진은 최적화된 룩업 알고리즘을 통한 소프트웨어 방식으로 구현되었으나, 처리해야 할 데이터가 폭주하면서 전용화된 룩업칩을 이용한 포워딩 엔진으로 대체되어 가고 있다. 그러나, 이러한 룩업칩 기반 패킷 포워딩 엔진은 가격이 비싼 것은 물론. 급변하는 통신 프로토콜에 적응하기 힘든 단점을 가지게 되었으며, 이로 인해서 최근에는 Network Processor 기반의 패킷 포워딩 엔진에 대한 개발이 활발해지고 있다. 본 연구소에서도 초고속광가입자망 사업에 적용되는 포워딩 엔진을 IBM의 2.5G Network Processor 인 NP4GS3 칩을 이용하고 있으며, GbE/POS/E-PON 등의 인터페이스를 지원하고 있다. 또한 본 사업에서는 가입자망에서의 Layer2 broadcasting시의 트래픽 폭주와 가입자간의 보안 기능 등을 지원하기 위해 VLAN 서비스를 적용할 예정이다. 본 논문에서는 일반적인 VLAN 기능에 대해서 알아보고, IBM NP4GS3에서 지원되는 VLAN 기능을 분석하였으며, 이를 토대로 NP4GS3 기반 패킷 포워딩 엔진에서 VLAN 구현 방안에 대하여 기술하였다.

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Performance Evaluation of a Cell Reassembly Mechanism with Individual Buffering in an ATM Switching System

  • Park, Gwang-Man;Kang, Sung-Yeol;Han, Chi-Moon
    • ETRI Journal
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    • v.17 no.1
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    • pp.23-36
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    • 1995
  • We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.

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Design of FEP(Front-End Processor) System for Information Exchange (정보교환을 위한 FEP시스템의 설계)

  • 강창언;이명수;정연호;이명호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.2
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    • pp.138-148
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    • 1988
  • In this paper, it is focused on the design of the FEP system that executes the access control programs instead of the hos processor. And so the FEP system improves the network flexibility and redues the installation costs of network. The design criterion of the FEP system is based on the ISDN construction which presents the information channel in thr future information society. The proposed hardwares and transmission softwares use the basic transmission rate of 64Kbps, and the contents of file service throuth this FEP system are listed by FTAM services.

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The training of convolution neural network for advanced driver assistant system

  • Nam, Kihun;Jeon, Heekyeong
    • International Journal of Advanced Culture Technology
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    • v.4 no.4
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    • pp.23-29
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    • 2016
  • In this paper, the learning technique for CNN processor on vehicle is proposed. In the case of conventional CNN processors, weighted values learned through training are stored for use, but when there is distortion in the image due to the weather conditions, the accuracy is decreased. Therefore, the method of enhancing the input image for classification is general, but it has the weakness of increasing the processor size. To solve this problem, the CNN performance was improved in this paper through the learning method of the distorted image. As a result, the proposed method showed improvement of approximately 38% better accuracy than the conventional method.

A Study on the Performance Analysis of Inter-Processor Communication Network for Digital Switching System (대용량 전자교환기 내부통신망 성능 분석에 관한 연구)

  • 최진규;이충근;이태원
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.7
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    • pp.1335-1345
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    • 1994
  • In this paper, the performance analysis of Inter-Processor Communication Network(IPCN) in a large-capacity digital switching system, TDX-10, is presented. The simulation model of IPCN is developed using discrete event model of SLAM II. The simulation results of maximum buffer length and mean waiting times at each node, and utilization of D-bus are derived. Finally, the maximum call handling capacity of IPCN is obtained by taking link speed into consideration.

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A Study of tasks scheduling algorithms for packet processing on network system with multi-processor multi-threaded architecture (멀티프로세서 멀티쓰레드 기반의 네트워크 시스템에서 패킷 처리 태스크의 스케줄링 알고리즘 성능 연구)

  • Kim, Chang-Kyoung;Kang, Yoon-Gu
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.23-26
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    • 2002
  • In this paper, we modelize several scheduling algorithms for real-time packet filtering tasks based on the multi-threaded multi-processor architecture for the network security system like the firewall and compare the performance of the algorithms by implementing the algorithms and doing a number of empirical tasks. As the matrices of the performance we use the idle factor and the packet transfer rate. We get the idle factors and the packet transfer rates according to the transfers of the packet sizes from 64 bytes to 1500 bytes.

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A Study on Real Time Monitoring of Tool Breakage in Milling Operation Using a DSP (DSP를 이용한 정면 밀링공구의 실시간 파단 감시방법에 관한 연구)

  • Baek, Dae-Kyun;Ko, Tae-Jo;Kim, Hee-Sool
    • Journal of the Korean Society for Precision Engineering
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    • v.13 no.6
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    • pp.168-176
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    • 1996
  • A diagnosis system which can monitor tool breakage and chipping in real time was developed using a DSP(Digital Signal Processor) board in face milling operation. AR modelling and band energy method were used to extract the feature of tool states from cutting force signals. Artificial neural network embedded on DSP board discriminates different patterns from features got after signal processing. The features extracted from AR modelling are more accurate for the malfunction of a process than those from band energy method, even though the computing speed of the former is slow. From the processed features, we can construct the real time diagnosis system which monitors malfunction by using a DSP board having a parallel processing capability.

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Estimating Pollutant Loading Using Remote Sensing and GIS-AGNPS model (RS와 GIS-AGNPS 모형을 이용한 소유역에서의 비점원오염부하량 추정)

  • 강문성;박승우;전종안
    • Magazine of the Korean Society of Agricultural Engineers
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    • v.45 no.1
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    • pp.102-114
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    • 2003
  • The objectives of the paper are to evaluate cell based pollutant loadings for different storm events, to monitor the hydrology and water quality of the Baran HP#6 watershed, and to validate AGNPS with the field data. Simplification was made to AGNPS in estimating storm erosivity factors from a triangular rainfall distribution. GIS-AGNPS interface model consists of three subsystems; the input data processor based on a geographic information system. the models. and the post processor Land use patten at the tested watershed was classified from the Landsat TM data using the artificial neural network model that adopts an error back propagation algorithm. AGNPS model parameters were obtained from the GIS databases, and additional parameters calibrated with field data. It was then tested with ungauged conditions. The simulated runoff was reasonably in good agreement as compared with the observed data. And simulated water quality parameters appear to be reasonably comparable to the field data.

A Japanese National Project for Superconductor Network Devices

  • Hidaka, M.
    • Progress in Superconductivity
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    • v.5 no.1
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    • pp.1-4
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    • 2003
  • A five-year project for Nb-based single flux quantum (SFQ) circuits supported by Japan's Ministry of Economy Trade and Industry (METI) in Japan was started in September 2002. Since April 2003, the New Energy and Industrial Technology Development Organization (NEDO) has supported this Superconductor Network Device Project. The aim of the project is to improve the integration level of Nb-based SFQ circuits to several ten thousand Josephson junctions, in comparison with their starting integration level of only a few thousand junctions. Actual targets are a 20 GHz dual processor module for the servers and a 0.96 Tbps switch module for the routers. Starting in April 2003, the Nb project was merged with SFQ circuit research using a high-T$_{c}$ superconductor (HTS). The HTS research targets are a wide-band AD converter for mobile-phone base stations and a sampling oscilloscope for wide-band waveform measurements.

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The Design and Implementation of Internet Outlet with Multiple User Interface Using TCP/IP Processor (TCP/IP프로세서를 이용한 다중 사용자 인터페이스 지원 인터넷 전원 콘센트의 설계 및 구현)

  • Baek, Jeong-Hyun
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.9
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    • pp.103-112
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    • 2012
  • Recently, the infrastructure to be connected to the internet is much provided, there is more and more need to connect electric or electronic products to the internet to monitor or control them remotely. However, most of the existing products lack the network interface, so it was very inconvenient to be connected to the internet. Therefore, this article designs and realizes the internet outlet allowing real-time scheduling that can control the power remotely on the internet by using the hardware TCP/IP processor. The realized product consumes low production cost because it can be realized by using the hardware TCP/IP processor and the 8-bit small microprocessor. In addition, the product can be used widely in both wired and wireless environments with a variety of user interface, including the dedicated control program which provides the environment configuration functions; embedded web service that enables the webpage to be saved on the external flash memory; Android smartphone application; motion recognition control environment that uses the OpenCV computer vision library, etc.