• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.56-63
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• 2000

In this paper, we design new high performance ATM switch architectures based on a Generalized Shuffle network(GSN). The GSN is a distributed network topology with the number of nodes in O(N). To improve the throughput of the switch, a layering strategy called Weaved GSN(WGSN). WGSN has an additional connection links between switching elements which locate in the same position of adjacent GSNs. The analysis and simulation are performed under uniform and full load conditions, and the results show that the proposed switch has better throughput and cell loss performance when compared with other banyan-based switch architectures known so far.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.506-513
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• 2001

The torque of an SRM depends on the phase current and derivative of inductance. But an SRM is difficult to control the desired torques because of saturation in magnetic circuit An SRM is controlled by parameters of input voltage, and switch on , off angle The switch on off angles of an SRM regulate the magnitude and shape of current waveform and decide the magnitude and shape of torque This paper proposes an the optimization control scheme by adjusting both the switch on an switch off angle . The switch off angles are decided by reference of efficiency using simulation and experiments. The switch on angles are decided by load torque , And the dwell angles are controlled for torque control and speed control using GA-neural network which is used to simulated the reasonable switching angle.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.485-492
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• 2003

This paper presents a new modified input buffered switch, which called a grouped input buffered (GIB) switch, to eliminate the influence of HOL blocking when using multiple input buffers in ATM switches. The GIB switch consists of grouped sub switches per a network stage. The switch gives extra paths and buffered switching elements between groups for transferring the blocked cells. As the result, the proposed model can reduce the effect by the HOL blocking and thereafter it enhances the performance of the switch. The simulation results show that the proposed scheme has good performance in comparison with previous works by using the parameters such as throughput, cell loss, delay and system power.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1822-1831
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• 2014

Micro-grid is connected to the main power grid through a static switch. One of the critical issues in micro-grids is protection which must disconnect the micro-grid from the network in short-circuit contingencies. Protective methods of micro-grid mainly follow the model of distribution system protection. This protection scheme suffers from improper operation due to the presence of single-phase loads, imbalance of three-phase loads and occurrence of power swings in micro-grid. In this paper, a new method which prevents from improper performance of static micro-grid protection is proposed. This method works based on artificial neural network (ANN) and able to differentiate short circuit from power swings by measuring impedance and the rate of impedance variations in PCC bus. This new technique provides a protective system with higher reliability.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.374-377
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• 2003

In this paper, a performance evaluation model of the Fat-Tree network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem in the switch network The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that use the multiple a$\times$b buffered crossbar switches. It is observed that both analysis and simulation results are match closely.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.738-748
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• 2002

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.211-218
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• 2015

This paper describes the implementation of the accelerated virtual switch using Intel DPDK(Data Plane Development Kit), and evaluates the virtual network functions of the virtual switch which is one of the most important components to build a virtual network for cloud computing. Nowadays, new information service platforms are appeared from the interconnection of intelligent IT systems like IoT(Internet of Things). And many companies want to use the new service platform for their new application service. The companies can apply there new service early which needs small investment and responses adaptively to the fast change of consumer environment. Using cloud computing technology, the new business service can be introduced as a commercial IT service for the time to market. In this study, an implementation and investigation were performed for the accelerated virtual switch, called Intel DPDK virtual switch, which is using multi processors in network interface card for virtual network functions. It can be useful for Internet-oriented companies to leverage the new cloud service and businesses for its creativeness.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.45-56
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• 2004

In this paper, we propose ATM switch architecture including ALL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of m cells which consist of ALL type 1. ALL type 2, ALL type 3/4 and ALL type 5 cells. We propose two switch fabric methods; One supports the ALL type 2 cell processing per input port, the other global ALL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. In this paper, the AAL Type 2 switch module which adapts the former method is designed using VHDL language and implemented in FPGA chip. The designed AAL Type 2 switch module operates at 52MHz. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.167-174
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• 2003

This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.