• Title/Summary/Keyword: Network Processor[1]

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Parallel Video Processing Using Divisible Load Scheduling Paradigm

  • Suresh S.;Mani V.;Omkar S. N.;Kim H.J.
    • Journal of Broadcast Engineering
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    • v.10 no.1 s.26
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    • pp.83-102
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    • 2005
  • The problem of video scheduling is analyzed in the framework of divisible load scheduling. A divisible load can be divided into any number of fractions (parts) and can be processed/computed independently on the processors in a distributed computing system/network, as there are no precedence relationships. In the video scheduling, a frame can be split into any number of fractions (tiles) and can be processed independently on the processors in the network, and then the results are collected to recompose the single processed frame. The divisible load arrives at one of the processors in the network (root processor) and the results of the computation are collected and stored in the same processor. In this problem communication delay plays an important role. Communication delay is the time to send/distribute the load fractions to other processors in the network. and the time to collect the results of computation from other processors by the root processors. The objective in this scheduling problem is that of obtaining the load fractions assigned to each processor in the network such that the processing time of the entire load is a minimum. We derive closed-form expression for the processing time by taking Into consideration the communication delay in the load distribution process and the communication delay In the result collection process. Using this closed-form expression, we also obtain the optimal number of processors that are required to solve this scheduling problem. This scheduling problem is formulated as a linear pro-gramming problem and its solution using neural network is also presented. Numerical examples are presented for ease of understanding.

A Japanese National Project for Superconductor Network Devices

  • Hidaka, M.
    • Progress in Superconductivity
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    • v.5 no.1
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    • pp.1-4
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    • 2003
  • A five-year project for Nb-based single flux quantum (SFQ) circuits supported by Japan's Ministry of Economy Trade and Industry (METI) in Japan was started in September 2002. Since April 2003, the New Energy and Industrial Technology Development Organization (NEDO) has supported this Superconductor Network Device Project. The aim of the project is to improve the integration level of Nb-based SFQ circuits to several ten thousand Josephson junctions, in comparison with their starting integration level of only a few thousand junctions. Actual targets are a 20 GHz dual processor module for the servers and a 0.96 Tbps switch module for the routers. Starting in April 2003, the Nb project was merged with SFQ circuit research using a high-T$_{c}$ superconductor (HTS). The HTS research targets are a wide-band AD converter for mobile-phone base stations and a sampling oscilloscope for wide-band waveform measurements.

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Performance Analysis for Base Station Controller in Mobile Communication Networks

  • Lim Seog-Ku
    • International Journal of Contents
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    • v.1 no.2
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    • pp.13-17
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    • 2005
  • Base Station Controller which belongs to IMT-2000(International Mobile Telecommunication - 2000) network has several types of structure for efficient control protocol. This difference of structure occurs two different protocols for call handling. Recently the need of IMT-2000 is highly increasing, so it is important to analyze the performance of processors and IPC(Inter-Processor Communication) module with structure of BSC and protocol difference. This paper presents the performance comparison of different types of BSC in view of processor utilization, waiting time, queue length and QoS(Quality of Service) through the simulation model.

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Study of Parallel Network Processor using Global Cache (글로벌 캐시를 이용한 네트워크 병렬 프로세서 구조 연구)

  • Park, Jae-Won;Chung, Won-Young;Kim, Hyun-Pil;Lee, Jung-Hee;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1B
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    • pp.80-85
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    • 2011
  • The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.

A Study on the Multiple Fault-Tolerant Multipath Multistage Interconnection Network (다중 고정이 허용되는 다중경로 다단상호접속망에 관한 연구)

  • 김대호;임채택
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.972-982
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    • 1988
  • In multiprocessor systems, there are Omega network and M network among various MIN's which interconnect the processor and memory modules. Both one-path Omega network and two-path M network are composed of Log2N stages. In this paper, Augmented M network (AMN) with 2**k+1 paths and Augmented Omega network (AON) with 2**k paths are proposed. The proposed networks can be acomplished by adding K stage(s) to M network and Omega network. Using destination tag, routing algorithm for AMN and AON becomes simple and multiple faults are tolerant. By evaluating RST(request service time) performance of AMN and AON with (Log2N)+K stages, we demonstrated the fact that MMIN (AMN) with 2**k+1 paths performs better than MMIN(AON) with 2**k+1. paths.

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Performance Evaluation of a Cell Reassembly Mechanism with Individual Buffering in an ATM Switching System

  • Park, Gwang-Man;Kang, Sung-Yeol;Han, Chi-Moon
    • ETRI Journal
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    • v.17 no.1
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    • pp.23-36
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    • 1995
  • We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.

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Estimating Pollutant Loading Using Remote Sensing and GIS-AGNPS model (RS와 GIS-AGNPS 모형을 이용한 소유역에서의 비점원오염부하량 추정)

  • 강문성;박승우;전종안
    • Magazine of the Korean Society of Agricultural Engineers
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    • v.45 no.1
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    • pp.102-114
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    • 2003
  • The objectives of the paper are to evaluate cell based pollutant loadings for different storm events, to monitor the hydrology and water quality of the Baran HP#6 watershed, and to validate AGNPS with the field data. Simplification was made to AGNPS in estimating storm erosivity factors from a triangular rainfall distribution. GIS-AGNPS interface model consists of three subsystems; the input data processor based on a geographic information system. the models. and the post processor Land use patten at the tested watershed was classified from the Landsat TM data using the artificial neural network model that adopts an error back propagation algorithm. AGNPS model parameters were obtained from the GIS databases, and additional parameters calibrated with field data. It was then tested with ungauged conditions. The simulated runoff was reasonably in good agreement as compared with the observed data. And simulated water quality parameters appear to be reasonably comparable to the field data.

Implementation of a Fieldbus System Based on EIA-709.1 Control Network Protocol (EIA-709.1 Control Network Protocol을 이용한 필드버스 시스템 구현)

  • Park, Byoung-Wook;Kim, Jung-Sub;Lee, Chang-Hee;Kim, Jong-Bae;Lim, Kye-Young
    • Journal of Institute of Control, Robotics and Systems
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    • v.6 no.7
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    • pp.594-601
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    • 2000
  • EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

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Adaptive Online Processor Management Algorithms for QoS sensitive Multimedia Data Communication (다양한 형태의 멀티미디어 데이터를 위한 통신 프로세서의 효율적 관리 방법에 대한 연구)

  • Kim, Sung-Wook;Kim, Sung-Chun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.1B
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    • pp.17-21
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    • 2007
  • In this paper, we propose new on-line processor management algorithms that manage heterogeneous multimedia services while maximizing energy efficiency. These online management mechanisms are combined in an integrated scheme for higher system performance and energy efficiency. The most important feature of our proposed scheme is its adaptability, flexibility and responsiveness to current network conditions. Simulation results clearly indicate the superior performance of our proposed scheme to strike the appropriate performance balance between contradictory requirements.

The Implementation of the IPC Network using the Reserved Bus Topology (통신 예약 버스 방식을 이용한 IPC 통신망 구성에 관한 연구)

  • 김호건;박영덕;김선형;조규섭;박병철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.1
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    • pp.28-40
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    • 1988
  • Nowadays, the needs for intelligence of communication equipments and the cost down of micro processor are showing a tendency to have multi0processor in a single system. In this paper, based on the Reserved Bus Topology which is propoed in "A study on he Communication Method between the adjacent processor", the software and hardware is designed and developed. And tha validity of this method and the utility of designed software and hardware functions are also verified through exepriments.epriments.

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