• 한국경영과학회지
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• 제18권1호
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• pp.45-54
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• 1993

Monitoring processor in a circuit switched network is considered. Monitoring processor monitors communication links offers a grade of service in each link to controller. Such an information is useful for an effective maintenance of system. Two links with asymmetric system parameters and multi-symmetric links are respectively considered. Each links is to be an independent M /M/ 1/ 1/ type. Markov modeling technique is used to represent a model of monitoring processor with FCFS steering protocol. Performance measures considered are ratio of monitored jobs in each link, availability of minitoring processor and throughput of virtual processor in each link. The value of the performance meausres are compared with existing and simulation results.

• 한국통신학회논문지
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• 제21권12호
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• pp.3144-3153
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• 1996

ATM switching system is made up of transport network and control newrk according to its functions. The control device, basic part of control network must be developed before developing any other functions, and control device must be stable and need high reliability. Out distributed ATM switching system consists of several ALSs that provides variable local call services, and an ACS that interconnect among several ALSs. Eech ALS has CCCP that takes charage of call and connection control functions, and ACS has an OMP that takes charge of OA&M(Operation, Administration and Maintenance) functios. In this paper, we analyzed the performance evaluation of control device that manipulate subscriber's call based on ITU-T Q.2931 standard protocol messages and Interprocessor communication messages. As a result of simulation when the number of ALS is under 22, as the call arrival rate increase the processor utilization of CCCP increase rapidly than that of OMP. When the number of ALS is incremented to 22, the processor utilization of CCCP is balanced with the of OMP, and when the number of ALS exceeds 22, the processor utiliztion of OMP increase rapidly. Also if messary processing time of OMP is 1.35 times that of CCCP, processor utilizations of CCCP and OMP is equal.

• Journal of Semiconductor Engineering
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• 제2권2호
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• pp.130-135
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• 2021

Recently, deep neural networks (DNNs) are actively used for action control so that an autonomous system, such as the robot, can perform human-like behaviors and operations. Unlike recognition tasks, the real-time operation is essential in action control, and it is too slow to use remote learning on a server communicating through a network. New learning techniques, such as reinforcement learning (RL), are needed to determine and select the correct robot behavior locally. In this paper, we propose an energy-efficient DNN processor with a LUT-based processing engine and near-zero skipper. A CNN-based facial emotion recognition and an RNN-based emotional dialogue generation model is integrated for natural HRI system and tested with the proposed processor. It supports 1b to 16b variable weight bit precision with and 57.6% and 28.5% lower energy consumption than conventional MAC arithmetic units for 1b and 16b weight precision. Also, the near-zero skipper reduces 36% of MAC operation and consumes 28% lower energy consumption for facial emotion recognition tasks. Implemented in 65nm CMOS process, the proposed processor occupies 1784×1784 um2 areas and dissipates 0.28 mW and 34.4 mW at 1fps and 30fps facial emotion recognition tasks.

• 전자공학회논문지A
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• 제33A권2호
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• pp.1-7
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• 1996

In this paper, we analyzed the packet blocking probability of a finite buffer in a network interface unit. In general, a network interface unit which provides a means of interface between the network and computer has a microprocessor and a protocol processor for the network access protocols. It also has a receive buffer for the arriving packets from the network which is served by the microprocessor with service interruption by the protocol processor. In this paper, we modeled the receive buffer as a discrete time server with service interruption, and obtained the packet blocking probability using the mini-slot approximation.

• 대한전자공학회논문지
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• 제22권6호
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• pp.114-123
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• 1985

이 논문은 packet switching 방식에 의한 공중 computer 통신망 개발에 관한 4편의 논문중 제 2부의 논문으로 제 1부의 KORNET의 개요 및 netwo.k managementcenter (NMC)개발에관한 논문에 이어 KO-RNET의 설계와 networhnode Processor(NNP)의 개발에 대해 기술한다. KORNET은 3개의 NNP와 하나의 NMC 로 일차 구성하였는데, NNP는 MC68000 microprocessor를 이용한 multiprocessor system으로 구현되었고, HMC는 중형 computer인 Mv/8000 system을 사용하여 개발하였다. KORNET에서의 packet service 방식은 virtual circuit(VC) 방식으로 하고 routing은 node나 선로의 상태변화에 쉽게 대처할 수 있는 분산적응방식(distributed adaptive routinB)을 사용하였다. 또한, buffo. management는 dy-namic sharing 방식을 채택하여 storage의 사용에 대한 효율성을 높였다. NNP system의 hardware는 modularity를 고려하여 확장이 용이하게 하였으며, software는 CCITT 권고사항 X.25, X.3, X.28, X.29등을 따라 구현하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.413-416
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• 2007

Use ot Intelligent devices that work on the ANSI/EIA 709.1 protocol is increasing. In this study an ANSI/EIA 709.1 protocol analyzer that can monitor and analyze the packets on LonWorks network is designed and developed. The device is based on TMS320LF2407A processor for decoding data packets, and uses XScale processor for sending data to the application program on PC. The application program has various analysis features as well as basic monitoring function. The developed device can be used for debugging purposes in development of any kind of LonWorks devices, and also it is useful in maintenance of LonWorks network or Lon Works devices.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.374-376
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• 2005

In this paper, we presented our implementation of 3DES and HMAC-MD5 processing functionality in Intel? IXP 2400 platform. It can be used as encryption and authentication engine for VPNs such as IPsec and SSL.

• 대한산업공학회지
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• 제40권1호
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• pp.135-139
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• 2014

In a connection-oriented packet switching network, the data communication starts after a virtual circuit is established between source and destination. The virtual circuit establishment time includes the queue waiting times in the direction from source to destination and the other way around. We use this two-way queueing delay to evaluate scheduling policies of a packet switching processor through simulation studies. In this letter, we also suggest user testing functions for the packet switching processor to manage virtual circuits. By detecting error causes, the user testing helps the packet switching processor provide reliable connection-oriented services.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• 대한임베디드공학회논문지
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• 제3권1호
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• pp.34-41
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• 2008

There are many researches to build up ubiquitous environment by the Ubiquitous Sensor Network(USN). These applications, such as home network, health care, natural environment and agricultural areas, are implemented by an embedded system. Their fields are gradually spreading. However the power consumption in its implementation plays an important role on the surrounding environment of the wireless network. In this paper, we design low power processor based sensor node platform for agricultural applications. We also compare its some performance with existing products.