• Title/Summary/Keyword: Network Processor[1]

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A Distributed Algorithmfor Weighted Shortest Path Problem (최단경로문제를 해결하는 효율적인 분산 알고리즘)

  • Park, Jeong-Ho;Park, Yun-Yong
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.1
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    • pp.42-48
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    • 1999
  • Consider the situation that informations necessary to solve a certain problem are distributed among processors on a network. It is called a distributed algorithm that in this situation each processor exchanges the message with adjacent processors to solve the problems. This paper proposes a distributed algorithm to solve the problem that constructs the weighted shortest path tree in an asynchronous network system. In general, a distributed algorithm is estimated by the number of messages(message complexity of the distributed algorithm proposed in this paper are O(n53) and O(nln) respectively. where n is the number of processors on the network.

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An Analysis for Efficient Appliance of TDL Protocol and IP on Link-K System (한국형전술데이터링크(Link-K)에서 TDL 프로토콜과 IP의 효과적인 적용방안 분석)

  • Jee, Seung-Bae
    • Journal of the Korea Institute of Military Science and Technology
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    • v.11 no.1
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    • pp.25-32
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    • 2008
  • In this paper, we propose how to efficiently apply IP and TDL(Tactical Datalink) protocol to the Link-K network for using their applications on the host system. We classify 3 kinds of communication method between IP network and TDL network. We explain the concepts of Like-to-Like communication (Link-K over IP, IP over Link-K) and Any-to-Any communication. We describe the characteristics and the implementation range of tactical datalink processor for each communication method.

Flood Search Algorithm with MFDL Path in Circuit-Switched Networks (회선 교환망에서 MFDL 경로를 이용한 Flood Search 알고리즘)

  • 박영철;이상철;은종관
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.3
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    • pp.360-371
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    • 1993
  • Flood search algorithm is known to be an effective routing mechanism for tactical application, since it provides high degree of survivability and robustness. But it is known that it has significant drawbacks with respect to the network efficiency [1]. We consider a tactical circuit-switched grid network with a maximum of four links and two priority classes of voice traffic, Using the minimum first-derivative length (MFDL) path, we improve the blocking probability performance of the circuit-switched network without increasing the call set-up time and processor loading of the algorithm.

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The Design of a Structure of Network Co-processor for SDR(Software Defined Radio) (SDR(Software Defined Radio)에 적합한 네트워크 코프로세서 구조의 설계)

  • Kim, Hyun-Pil;Jeong, Ha-Young;Ham, Dong-Hyeon;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.2A
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    • pp.188-194
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    • 2007
  • In order to become ubiquitous world, the compatibility of wireless machines has become the significant characteristic of a communication terminal. Thus, SDR is the most necessary technology and standard. However, among the environment which has different communication protocol, it's difficult to make a terminal with only hardware using ASIC or SoC. This paper suggests the processor that can accelerate several communication protocol. It can be connected with main-processor, and it is specialized PHY layer of network The C-program that is modeled with the wireless protocol IEEE802.11a and IEEE802.11b which are based on widely used modulation way; OFDM and CDM is compiled with ARM cross compiler and done simulation and profiling with Simplescalar-Arm version. The result of profiling, most operations were Viterbi operations and complex floating point operations. According to this result we suggested a co-processor which can accelerate Viterbi operations and complex floating point operations and added instructions. These instructions are simulated with Simplescalar-Arm version. The result of this simulation, comparing with computing only one ARM core, the operations of Viterbi improved as fast as 4.5 times. And the operations of complex floating point improved as fast as twice. The operations of IEEE802.11a are 3 times faster, and the operations of IEEE802.11b are 1.5 times faster.

DSP-Based Micro-Modem for Underwater Acoustic Communications (DSP 기반 초소형 수중 음향통신 모뎀)

  • Lee, Dongsoo;Lee, Sangmin;Park, Sung-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.3
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    • pp.275-281
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    • 2014
  • Recently, the need for various underwater application systems targeting efficient resource exploration and aquatic ecosystem monitoring is rapidly increasing in littoral sea and inland waters. In this paper, we focus on the research and development of digital module of acoustic micro modem which can be used for underwater mobile communication systems and underwater sensor network systems. Specifically, a digital module of acoustic modem embedding digital signal processor is designed and implemented. On top of the developed hardware platform, physical layer frame generation and recovery and channel coding algorithms are mounted and tested in a water tank and a pond to verify its functionality and performance. According to experimental results, less than 1 percent of total computational power is consumed in the processing of frame control and convolutional code with the data rate of 1 kbps. Thus, the performance of micro modem could be improved by loading efficient baseband algorithms into the processor while maintaining the implemented hardware.

Analyses of Crypto Module for Gbps VPN System

  • Kim, Jung-Tae;Han, Jong-Wook
    • Journal of information and communication convergence engineering
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    • v.1 no.4
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    • pp.213-216
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    • 2003
  • A VPN is widely used in a communications environment which access is controlled to permit peer connections only within a defined community of interest. It is constructed through some form of partitioning of a common underlying communication medium, where this underlying communications medium provides services to the network on a non-exclusive basis. In this paper, we have analyzed a variety of architecture to implement Giga bps VPN system. The proposed architecture will satisfy the needs of clients who adopt Giga bps VPN system in the various environments.

Performance Analysis of Communication Processor Based on Industrial Network (산업용 네트워크기반 통신 프로세서의 트래픽 처리 성능 분석)

  • Yoon, Mihee;Park, Young;Kim, Dongwon
    • Annual Conference of KIPS
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    • 2013.05a
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    • pp.782-784
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    • 2013
  • 스마트 자동차, 선박 및 공장 자동화와 같은 산업 분야에서 이더넷 기반 산업 네트워크의 연구가 추진되고 있다. IEEE802.1AVB와 같은 실시간 이더넷 프로토콜을 살펴보고 산업용 스위치드 이더넷 기반 통신 프로세서에서 우선 순위 트래픽을 처리하는 큐 모델링과 성능 분석을 수행한다.

Implementation of Remote Image Surveillance for Mobile Robot Platform based on Embedded Processor (주행용 로봇 플랫폼을 위한 임베디드 프로세서 기반 원격영상감시 시스템 구현)

  • Han, Kyong-Ho;Yun, Hyo-Won
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.1
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    • pp.125-131
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    • 2009
  • In this paper, we proposed the remote visual monitoring system on mobile robot platform. The proposed system is composed of ARM9 core PXA255 processor, micro CMOS camera and wireless network and the captured visual image is transmitted via 803.11b/g wireless LAN(WLAN) for remote visual monitoring operations. Robot platform maneuvering command is transmitted via WLAN from host and the $640{\times}480$, $320{\times}240$ pixel fixed visual image is transmitted to host at the rate of $3{\sim}10$ frames per second. Experimental system is implemented on Linux OS base and tested for remote visual monitoring operation and verified the proposed objects.

An Efficient Parallelized Algorithm of SEED Block Cipher on Cell BE (CELL 프로세서를 이용한 SEED 블록 암호화 알고리즘의 효율적인 병렬화 기법)

  • Kim, Deok-Ho;Yi, Jae-Young;Ro, Won-Woo
    • The KIPS Transactions:PartA
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    • v.17A no.6
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    • pp.275-280
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    • 2010
  • In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

Analysis of Delay Time in the Personal Communications Exchange (개인통신교환기의 지연시간 분석)

  • Jang, Hee-Seon;Suh, Jae-Jun;Lim, Seog-Ku;Yu, Jea-Hoon;Lee, Yoon-Ju
    • IE interfaces
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    • v.9 no.3
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    • pp.180-193
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    • 1996
  • 본 논문에서는 시뮬레이션 모델을 통해 호유형뿐만 아니라 개인통신서비스에서 필수적인 핸드오버 및 위치등록 등의 모든 트래픽 유형을 고래했을 때 개인통신교환기(PCX : Personal Commuincations Exchange)에서의 지연시간을 분석하며, 지연시간에 대한 결과와 프로세서의 이용율로부터 개인통신교환기의 호처리 및 이동성처리용량을 분석하고 그에 따른 가입자의 수용능력을 추정한다. IPC(Inter-Processor Communications) 메시지의 송수신시간 및 메시지의 처리시간등 교환기 제어계의 성능분석에 필요한 입력 파라미터 값은 기존 ISDN(Integrated Services Digital Network) 및 CMS-MX(CDMA Mobile System-Mobile Exchange) 교환기의 측정자료를 이용하였다. 시뮬레이션 분석결과 PCX 교환기의 호처리 성능은 주로 번호번역 기능을 담당하는 프로세서인 NTP(Number Translation Processor)의 용량에 의해 결정되며, 가입자 밀도가 1,500명$/km^2$인 경우 호처리용량은 약 42만 BHC(Busy Hour Call Completion)로 추정되었고, 이에 상응하는 핸드오버 및 위치등록 처리용량은 각각 시간당 약 2만 6천히 및 40만 6천회로 나타났다. 이것은 가입자당 호처리 부하가 1.6BHC일 경우, 약 15만 7천 가입자를 수용할 수 있는 용량에 해당한다.

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