• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.350-359
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• 2011

Fast developments of broadcasting technologies since 1990s enabled not only High Definition Television service providing high quality audiovisual contents at home but also mobile broadcasting service providing audiovisual contents to high speed moving vehicle. Terrestrial Digital Multimedia Broadcasting (T-DMB) is one of the technologies developed for mobile broadcasting service, which has been successfully commercialized. One of the major technical breakthroughs achieved by T-DMB in addition to robust vehicular reception is an adoption of framework based on MPEG-4 System. It naturally enables integrated interactive data services by using Binary Format for Scene (BIFS) technology for scene description and representation of graphics object and Object Descriptor Framework representing multimedia service components as objects. T-DMB interactive data service has two fundamental limitations. Firstly, graphic data for interactive service should be always overlaid on top of a video not to be rendered out of it. Secondly, data for interactive service is only received by broadcasting channel. These limitations were considered as general in broadcasting systems. However, they are being considered as hard limitations for personalized data services using location information and user characteristics which are becoming widely used for data services of smart devices in these days. In this paper, the architecture of T-DMB hybrid data service is proposed which is utilizing broadcasting network, wireless internet and local storage for delivering BIFS data to overcome these limitations. This paper also presents hybrid BIFS technology to implement T-DMB hybrid data service while maintaining backward compatibility with legacy T-DMB players.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.11
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• pp.1094-1103
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• 2012

Recently, software industry regarding national defense increases system development of distributed simulation system of M&S based to overcome limit of resource and expense. It is one of key technologies for offering of mutual validation among objects and reuse of objects which are discussed for developing these systems. RTI, implementation of HLA interface specification as software providing these technologies uses Federation Object Model for exchanging information with joined federates in the federation and each federate has a characteristic that is supposed to have identical FOM in the federation. This technology is a software which is to provide the core technology which was suggested by the United state's military M&S standard framework. Simulator, virtual simulation, and inter-connection between military weapons system S/W which executes on network which is M&S's core base technology, and it is a technology which also can be used for various inter-connection between S/W such as game and on-line phone. These days although RTI is used in military war game or tactical training unit field, there is none in Korea. Also, it is used in mobile-game, distribution game, net management, robot field, and other civilian field, but the number of examples are so small and informalized. Through this developing project, we developed the core technique and RTI software and provided performance of COTS level to improve communication algorithms.

• Ecology and Resilient Infrastructure
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• v.5 no.1
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• pp.35-44
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• 2018

Social, economic and environmental problems caused by rapid urbanization have been recently overcome by various civic participation projects. Local governance and resident - led partnership through field - based cooperative operating systems from urban regeneration to village projects are considered success factors. Among these, the village greening project which directly affects the residents and requires spontaneity requires the role and cooperation of the various participating actors due to the sharing of public space and private space. Social capital plays a key role in the sustainability and participation of the above - mentioned business as a relational capital centered on trust and participation, network and norms. Therefore, empirical research is needed. In this study, basic research was carried out to build a formation model of social capital in participation - type greening project expanding urban green space system to living area. We analyzed the elements of participation, the components of business progress, and the factors of social capital formation through literature review and in - depth interviews with participating experts. The purpose of this study is to provide basic data of social capital formation model for analyzing sustainability and activation strategies in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1027-1034
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• 2005

IEEE802.15.4a, which is started to realize the PHY layer including high precision ranging/positioning and low data rate communication functions, requires a simple and low power consumable transceiver architecture. To satisfy this requirements, the simple noncoherent on-off keying (OOK) UWB transceiver with the parallel energy window banks (PEWB) giving high precision signal processing interface is proposed. The flexibility of the proposed system in multipath fading channel environments is acquired with the pulse and bit repetition method. To analyze the bit error rate (BER) performance of this proposed system, a noise model in receiver is derived with commonly used random variable distribution, chi-square. BER of $10^{-5}$ under the line-of-sight (LOS) residential channel is achieved with the integration time of 32 ns and signal to noise ratio (SNR) of 15.3 dB. For the non-line-of-sight (NLOS) outdoor channel, the integration time of 72 ns and SNR of 16.2 dB are needed. The integrated energy to total received energy (IRR) for the best BER performance is about $86\%$.

• The Journal of the Acoustical Society of Korea
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• v.24 no.8
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• pp.498-504
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• 2005

We introduce a Korean speech recognition platform (ECHOS) developed for education and research Purposes. ECHOS lowers the entry barrier to speech recognition research and can be used as a reference engine by providing elementary speech recognition modules. It has an easy simple object-oriented architecture, implemented in the C++ language with the standard template library. The input of the ECHOS is digital speech data sampled at 8 or 16 kHz. Its output is the 1-best recognition result. N-best recognition results, and a word graph. The recognition engine is composed of MFCC/PLP feature extraction, HMM-based acoustic modeling, n-gram language modeling, finite state network (FSN)- and lexical tree-based search algorithms. It can handle various tasks from isolated word recognition to large vocabulary continuous speech recognition. We compare the performance of ECHOS and hidden Markov model toolkit (HTK) for validation. In an FSN-based task. ECHOS shows similar word accuracy while the recognition time is doubled because of object-oriented implementation. For a 8000-word continuous speech recognition task, using the lexical tree search algorithm different from the algorithm used in HTK, it increases the word error rate by $40\%$ relatively but reduces the recognition time to half.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.5
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• pp.219-230
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• 2017

General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.235-245
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• 2005

The rapid development of computer network technology has brought the Internet as the major infrastructure to our society. But the rapid increase in malicious computer intrusions using such technology causes urgent problems of protecting our information society. The recent trends of the intrusions reflect that the intruders do not break into victim host directly and do some malicious behaviors. Rather, they tend to use some automated intrusion tools to penetrate systems. Most of the unknown types of the intrusions are caused by using such tools, with some minor modifications. These tools are mostly similar to the Previous ones, and the results of using such tools remain the same as in common patterns. In this paper, we are describing design and implementation of attacker-traceback system, which traces the intruder based on the multi-agent architecture. The system first applied SOM to classify the unknown types of the intrusion into previous similar intrusion classes. And during the intrusion analysis stage, we formalized the patterns of the tools as a knowledge base. Based on the patterns, the agent system gets activated, and the automatic tracing of the intrusion routes begins through the previous attacked host, by finding some intrusion evidences on the attacked system.

• KIPS Transactions on Software and Data Engineering
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• v.9 no.5
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• pp.169-176
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• 2020

Recently, deep neural networks (DNNs) have brought revolutions to many mobile and embedded devices by providing human-level machine intelligence for various applications. However, high inference accuracy of such DNNs comes at high computational costs, and, hence, there have been significant efforts to reduce computational overheads of DNNs either by compressing off-the-shelf models or by designing a new small footprint DNN architecture tailored to resource constrained devices. One notable recent paradigm in designing small footprint DNN models is sharing parameters in several layers. However, in previous approaches, the parameter-sharing techniques have been applied to large deep networks, such as ResNet, that are known to have high redundancy. In this paper, we propose a parameter-sharing method for already parameter-efficient small networks such as ShuffleNetV2. In our approach, small templates are combined with small layer-specific parameters to generate weights. Our experiment results on ImageNet and CIFAR100 datasets show that our approach can reduce the size of parameters by 15%-35% of ShuffleNetV2 while achieving smaller drops in accuracies compared to previous parameter-sharing and pruning approaches. We further show that the proposed approach is efficient in terms of latency and energy consumption on modern embedded devices.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.115-121
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• 2015

In this paper, we proposed an iterative data-flow optimal scheduling algorithm based on genetic algorithm for high-performance multiprocessor. The basic hardware model can be extended to include detailed features of the multiprocessor architecture. This is illustrated by implementing a hardware model that requires routing the data transfers over a communication network with a limited capacity. The scheduling method consists of three layers. In the top layer a genetic algorithm takes care of the optimization. It generates different permutations of operations, that are passed on to the middle layer. The global scheduling makes the main scheduling decisions based on a permutation of operations. Details of the hardware model are not considered in this layer. This is done in the bottom layer by the black-box scheduling. It completes the scheduling of an operation and ensures that the detailed hardware model is obeyed. Both scheduling method can insert cycles in the schedule to ensure that a valid schedule is always found quickly. In order to test the performance of the scheduling method, the results of benchmark of the five filters show that the scheduling method is able to find good quality schedules in reasonable time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.