• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.504-510
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• 2015

This paper presents a power and area efficient SAR ADC for multi-channel near threshold-voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive-array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi-channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively.

• Journal of IKEEE
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• v.22 no.4
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• pp.1218-1221
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• 2018

This paper presents a low-power 0.6-V 10-bit 200-kS/s double rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme allows input signal with 4 times power which is compared with conventional one by applying proposed rail-to-rail scheme, and that improves signal-to-noise ratio(SNR) of NTV SAR ADCs. The prototype was designed using 65-nm CMOS technology. At a 0.6-V supply and $2.4-V_{pp}$ (differential) and 200-kS/s, the ADC achieves an SNDR of 59.87 dB and consumes 364.5-nW. The ADC core occupies an active area of only $84{\times}100{\mu}m^2$.