• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.78-81
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• 2015

Pure ZnO and ZnO nanowires doped with 3 wt.% Ga (‘3GZO’) were grown by pulsed laser deposition in a furnace system. The doping of Ga in ZnO nanowires was analyzed by observing the optical and chemical properties of the doped nanowires. The diameter and length of nanowires were under 200 nm and several ${\mu}m$, respectively. Changes of significant resistance were observed and the sensitivities of ZnO and 3GZO nanowires were compared. The sensitivities of ZnO and 3GZO nanowire sensors measured at 300℃ for 1 ppm of ethanol gas were 97% and 48%, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.273-273
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• 2010

Recently, extensive research on hetero-junction arrays has been reported owing to its unique band gaps dissimilar to that of homo-junctions. These hetero-junction devices can be used in laser, solar cells, and various sensors. We report on the facile method to fabricate SWCNTs/SnO2 nanowires hetero-junction arrays on flexible polyimide substrate. Each SWCNT field effect transistor (FET) and SnO2 nanowire FET exhibits the purely p- and n-type charactersistics with ohmic contact properties. Such formed pn-junctions showed rectification behaviors reproducibly with a rectification ratio of ${\sim}3{\times}103$ at 1 V and ideality factors about 12. The pn-junctions also showed a good gate modulation behavior.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.149-150
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• 2006

A ZnO nanowire-based FET is fabricated m this study on a flexible substrate of PES. For the flat and bent flexible substrates, the current ($I_D$) versus drain-source bias voltage ($V_{DS}$) and $I_D$ versus gate voltage ($V_G$) results are compared. The flat band was Ion/Ioff ratio of ${\sim}10^7$, a transconductance of 179 nS and a mobility of ~10.104 cm2/Vs at $V_{DS}$ =1 V. Also bent to a radius curvature of 0.15cm and experienced by an approximately strain of 0.77 % are exhibited an Ion/Ioff ratio of ${\sim}10^7$, a transconductance of ~179 nS and a mobility of ${\sim}10.10 cm^2/Vs$ at $V_{DS}$ = 1V. The electrical characteristics of the FET are not changed very much. although the large strain is given on the device m the bent state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.13-14
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• 2005

ZnO 단일 나노선 field effect transistor (FET) 소자의 2단자 전류-전압 특성을 조사해 보면 n-type 반도체 특성이 나타남을 알 수 있다. 그러나 2단자로 측정 할 경우 반도체 나노선과 금속 전극사이에 존재하는 접촉저항의 영향이 필연적으로 포함된다. 따라서 측정한 결과가 나노선에 의해서 나타나는 고유한 특성인지 접촉저항의 원인이 되는 에너지 장벽의 성질인지 명확히 밝힐 필요가 있다. 그래서 이번 연구에서는 4단자 측정방법을 이용하여 접촉저항 성분을 배제한 소자의 고유한 성질을 밝혀낼 뿐만 아니라, 이것을 2단자의 결과와 비교함으로써 접촉점에서 나타나는 에너지 장벽의 특징도 파악해 낼 수 있었다. 실험에서 사용된 ZnO FET 소자의 경우, 접촉점에서 생기는 에너지 장벽을 터널링을 통해 극복하는 것으로 분석되었고 이는 온도 변화에 따른 4 단자 및 2 단자 전류-전압 측정을 통해 확인될 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.398-403
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• 2017

본 연구에서는 gate-all-around(GAA) 수직 나노선 Field-Effect Transistor(FET)의 소스/드레인 반도체/실리사이드 접합에 존재하는 Schottky 장벽이 트랜지스터의 DC특성에 미치는 영향에 대하여 조사하였다. Non-Equilibrium Green's Function와 Poisson 방정식 기반의 시뮬레이터를 사용하여, Schottky 장벽의 위치와 높이, 그리고 채널 단면적의 크기에 따른 전류-전압 특성 곡선과 에너지 밴드 다이어그램을 통해 분석을 수행하였다. 그 결과, 드레인 단의 Schottky 장벽은 드레인 전압에 의해 장벽의 높이가 낮아져 전류에 주는 영향이 작지만, 소스 단의 Schottky 장벽은 드레인 전압과 게이트 전압으로 제어가 불가능하여 외부에서 소스 단으로 들어오는 캐리어의 이동을 방해하여 큰 DC성능 저하를 일으킨다. 채널 단면적 크기에 따른 DC특성 분석 결과로는 동작상태의 전류밀도는 채널의 폭이 5 nm 일 때까지는 유지되고, 2 nm가 되면 그 크기가 매우 작아지지만, 채널 단면적은 Schottky 장벽에 영향을 끼치지 못하였다. 본 논문의 분석 결과로 향후 7 nm technology node 에 적용될 GAA 수직 나노선 FET의 소자 구조 설계에 도움이 되고자 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.565-565
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• 2012

그래핀(Graphene) 기반의 전계효과 트랜지스터(Field effect transistor) 응용에 있어, 가장 핵심적인 도전과제중 하나는 에너지 밴드갭(Energy bandgap)을 갖는 그래핀 채널의 제작이다. 그래핀은 에너지 밴드갭이 존재하지 않는 반금속(semi metal)의 특성을 지니고 있어, 그 본래의 물리적 특성을 지니고서는 소자구현에 어려움이 있다. 그러나 폭이 수~수십 나노미터인 그래핀 나노리본(Graphene nanoribbon)의 경우 양자구속효과(Quantum confinement effect)에 의하여 에너지 밴드갭이 형성되며, 갭의 크기는 리본의 폭에 반비례한다는 연구결과가 보고된 바 있다. 이러한 이유에서, 효과적이며 실현가능한 그래핀 나노리본의 제작은 필수적이다. 본 연구에서는 은 나노 와이어(Ag nanowire)를 기반으로 한 그래핀 나노리본의 합성을 연구하였다. 은 나노와이어를 열화학 기상증착법(Thermal chemical vapor deposition)을 이용, 아세틸렌(Acetylene, C2H2) 가스를 탄소공급원으로 하여 그래핀을 나노와이어 표면에 합성하였다. 합성과정에서 구조에 영향을 미치는 요인인 합성온도와 가스의 비율, 압력 등을 조절하여 최적화된 합성조건을 확립하였다. 합성된 나노리본의 특성을 라만분광법(Raman spectroscopy)과 주사전자 현미경(Scanning electron microscopy), 투과전자현미경(Transmission electron microscopy), 원자힘 현미경(Atomic force microscopy)를 통하여 분석하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.549-549
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• 2012

Early detection of cancer biomarkers in the blood is of vital importance for reducing the mortality and morbidity in a number of cancers. From this point of view, immunosensors based on nanowire (NW) and carbon nanotube (CNT) field-effect transistors (FETs) that allow the ultra-sensitive, highly specific, and label-free electrical detection of biomarkers received much attention. Nevertheless 1D nano-FET biosensors showed high performance, several challenges remain to be resolved for the uncomplicated, reproducible, low-cost and high-throughput nanofabrication. Recently, two-dimensional (2D) graphene and reduced GO (RGO) nanosheets or films find widespread applications such as clean energy storage and conversion devices, optical detector, field-effect transistors, electromechanical resonators, and chemical & biological sensors. In particular, the graphene- and RGO-FETs devices are very promising for sensing applications because of advantages including large detection area, low noise level in solution, ease of fabrication, and the high sensitivity to ions and biomolecules comparable to 1D nano-FETs. Even though a limited number of biosensor applications including chemical vapor deposition (CVD) grown graphene film for DNA detection, single-layer graphene for protein detection and single-layer graphene or solution-processed RGO film for cell monitoring have been reported, development of facile fabrication methods and full understanding of sensing mechanism are still lacking. Furthermore, there have been no reports on demonstration of ultrasensitive electrical detection of a cancer biomarker using the graphene- or RGO-FET. Here we describe scalable and facile fabrication of reduced graphene oxide FET (RGO-FET) with the capability of label-free, ultrasensitive electrical detection of a cancer biomarker, prostate specific antigen/${\alpha}$ 1-antichymotrypsin (PSA-ACT) complex, in which the ultrathin RGO channel was formed by a uniform self-assembly of two-dimensional RGO nanosheets, and also we will discuss about the immunosensing mechanism.

• Journal of IKEEE
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• v.13 no.2
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• pp.126-131
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• 2009

To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.