• Journal of Sensor Science and Technology
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• v.18 no.5
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• pp.327-336
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• 2009

최근 인류의 삶의 질 향상에 따라 건강하고, 쾌적하고, 편안한 삶을 살기 위한 많은 노력이 진행되고 있다. 센서는 이러한 삶의 질 향상을 위해서 필수불가결한 요소 중 하나이며, 고성능의 지능화된 센서가 요구되고 있어, 앞으로 이에 대한 수요는 더욱 증대될 것으로 생각된다. 최근의 센서 연구 개발 방향은 센서에 기능을 부여하는 기능성 재료가 중요한 요소로 더욱 부각되고 있으며, 특히, 다양한 성분과 형태로 존재하는 나노 기능 재료는 기존의 벌크 재료와는 차별화된 독특한 물리, 화학, 기계, 광학적 특성을 갖고 있어 더욱 주목받고 있다. 최근 기존의 나노 입자 연구에서 더욱 발전하여 서로 적용하기 위한 나노선이나 CNT를 포함한 나노튜브, 나노 복합재료 등의 연구가 매우 활발하다. 본 논문에서는 이러한 나노 재료를 이용한 가스 센서, 수질 센서, 바이오 센서, 광 센서 그리고 물리 센서 등 최신 나노 센서 연구개발 동향을 살펴보았으며, 미래 센서기술 발전방향 중 하나로서 나노 재료에 의한 센서의 고기능화 및 극소형화가 매우 중요한 부분으로 활용될 것으로 예측되었다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.103-107
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• 2023

To solve the reliability problem of organic devices that are often used outdoors, multifunctional gas barriers that block reactive gases such as moisture and oxygen and reflect harmful light such as ultraviolet rays are needed. In this study, ALD nanolaminate-based optically functional n-DBR was developed to overcome the poor gas permeability of polymer substrates and protect organic devices from harmful light. n-DBR not only achieved a WVTR of 8.76 × 10^-6 g·m^-2·day^-1, but also showed a visible light transmittance of 94.3% and an ultraviolet ray blocking ability of 2.67%. In particular, n-DBR based on a nanolaminate structure maintained its permeability characteristics even in a high temperature and high humidity environment despite being used as a layer of Al₂O₃. This functional barrier Structure can not only be used as a functional encapsulation barrier for the reliability of organic devices, but can also be used as a tinting film for vehicles.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.35-39
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• 2009

A novel Helmholtz coil inductively coupled plasma(H-ICP) etcher is proposed and characterized for deep nano-scale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about $5{\times}10^{11}/cm^3$, and the electron temperature was about 2-3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of $HeO_2$. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.1-6
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• 2004

Effective gate resistance, extracted by direct extraction method, is analyzed among various gate length, in nanoscale MOSFET for RFIC. Extracted effective gate resistance is compared to measured data and verified with simplified model. Extracted parameters are accurate to 10GHz. In the same process technology effect has a different kind of gate voltage dependency and frequency dependency compared with general effective gate resistance. Particularly, the characteristic of effective gate resistance before and after threshold voltage is noticeable. When gate voltage is about threshold voltage, effective gate resistance is abnormally high. This characteristic will be an important reference for RF MOSFET modeling using direct extraction method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1591-1593
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• 2008

The tubular field emission lamp (FEL) was developed using a wire type carbon-nano-structure emitter called CNX The luminous efficiency of the tubular FEL (diode type, diameter: ${\varphi}15.5mm$, length: 200mm) has already achieved around 45lm/W and we expect to achieve over 60lm/W within the year.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.727-730
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• 2003

Thin tin oxide film with nano-size particle was prepared on silicon substrate by hydrothermal synthetic method and successive sol-gel spin coating method. The fabrication method of tin oxide film with ultrafine nano-size crystalline structure was tried to be applied to fabrication of micro gas sensor array on silicon substrate. The tin oxide film on silicon substrate was well patterned by chemical etching upto 5${\mu}{\textrm}{m}$width and showed very uniform flatness. The tin oxide film preparation method and patterning method were successfully applied to newly proposed 2-dimensional micro sensor fabrication.

• The Optical Journal
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• s.125
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• pp.22-23
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• 2010

1970년대 중반 일본에서 만들어진 메카트로닉스(Mechatronics)라는 용어는 기계공학(Mechanics)과 전자공학(Electronics)의 합성어로 1980년대 이후 전세계적으로 널리 사용되었다. 이후 컴퓨터 기술의 급속한 발전에 힘입어 메카트로닉스는 로봇, 공장자동화, CNC공작기계 등 현대산업의 근간을 이루는 핵심 기술로 자리매김 하였다. 최근에는 학문의 경계를 허무는 작업들이 더욱 속도를 내고 있는 가운데, 생활에서 늘 접하는 휴대폰, TV, 빔프로젝트 등의 제품에 시각적 신호를 창출하기 위한 광학적 요소가 결합되고 있다. 이를 우리는 옵토메카트로닉스(Optomechatronics)라는 영역으로 분류한다. 여기에 생체공학(Bionics)과 나노기술(Nano technology)의 결합을 필요로 하는 제품들이 또한 바이오옵토메카트로닉스(Bio-Optomechatronics)또는 나노바이오 옵토메카트로닉스(Nano-Bioopmechatronics)등의 새로운 영역 창출을 준비하고 있다.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.120-120
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• 2011

Graphene is a carbon based material and it has great potential of being utilized in various fields such as electronics, optics, and mechanics. In order to develop graphene-based logic systems, graphene field-effect transistor (GFET) has been extensively explored. GFET requires supporting devices, such as volatile memory, to function in an embedded logic system. As far as we understand, graphene has not been studied for volatile memory application, although several graphene non-volatile memories (GNVMs) have been reported. However, we think that these GNVM are unable to serve the logic system properly due to the very slow program/read speed. In this study, a GVM based on the GFET structure and using an engineered graphene channel is proposed. By manipulating the deposition condition, charge traps are introduced to graphene channel, which store charges temporarily, so as to enable volatile data storage for GFET. The proposed GVM shows satisfying performance in fast program/erase (P/E) and read speed. Moreover, this GVM has good compatibility with GFET in device fabrication process. This GVM can be designed to be dynamic random access memory (DRAM) in serving the logic systems application. We demonstrated GVM with the structure of FET. By manipulating the graphene synthesis process, we could engineer the charge trap density of graphene layer. In the range that our measurement system can support, we achieved a high performance of GVM in refresh (>10 ${\mu}s$) and retention time (~100 s). Because of high speed, when compared with other graphene based memory devices, GVM proposed in this study can be a strong contender for future electrical system applications.