• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.35-40
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• 2010

NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Information and Communications Magazine
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• v.28 no.9
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• pp.58-68
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• 2011

본 고에서는 최근 다양한 분야에서 활용되고 있는 NAND flash 메모리 소자를 위한 오류정정 방식에 대한 동향을 소개하고자 한다. 먼저, NAND flash 메모리의 오류가 발생하는 원인을 소개하고 현재 사용되고 있는 오류정정 부호들의 소개 및 가까운 미래의 NAND flash 메모리에서 예상되는 오류 발생원인 및 이에 대처하기 위해 연구가진행 중인 오류정정 부호설계기술들에 대하여 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.7
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• pp.515-519
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• 2009

As the application fields of sensor nodes are getting diverse these days, it is required to have a way of collecting various data that is suitable for these application fields. In the case that the real-time surveillance over the data is unnecessary, present data collecting methods, which collect and transfer the data directly, can cause a waste of energy and data loss, A new method that store the collected data in a local storage and acquire them by query later on is required for nonreal-time applications. NAND flash has energy efficiency and large capacity so it is suitable for sensor nodes, Sensor nodes support 4-10 KBytes small sized memory and it is hard to build an effective file system since NAND Flash doesn't support overwriting NAND flash. This paper discusses an implementation of NAND Flash file system in sensor node environments. The file system makes long-term data collecting possible by reducing transmission cost. It is expected that this file system will play a central role in sensor network environments as it can be applied to various fields which call for long term data collecting.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Journal of Digital Contents Society
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• v.16 no.4
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• pp.535-543
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• 2015

Recently, NAND flash based storage devices are being used as a storage device in various fields through hiding the limitations of NAND flash memory and maximizing the advantages. In particular, those storage devices contain a software layer called Flash Translation Layer(FTL) to hide the "erase-before-write" characteristics of NAND flash memory. FTL includes the metadata for managing the data requested from host. That metadata is stored in internal memory because metadata is very frequently accessed data for processing the requests from host. Thus, if the power-loss occurs, all data in memory is lost. So metadata management scheme is necessary to store the metadata periodically and to load the metadata in the initialization step. Therefore we proposed the scheme which satisfies the core requirements for metadata management and efficient operation. And we verified the efficiency of proposed scheme by experiments.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.