• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.333-337
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• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.251-255
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• 2008

In most file systems, if a file is deleted, only the metadata of the file is deleted or modified and the file's data is still stored on the physical media. Some users require that deleted files no longer be accessible. This requirement is more important in embedded systems that employ flash memory as a storage medium. In this paper, we propose a secure deletion method for NAND flash file system and apply the method to YAFFS. Our method uses encryption to delete files and forces all keys of a specific file to be stored in the same block. Therefore, only one erase operation is required to securely delete a file. Our simulation results show that the amortized number of block erases is smaller than the simple encryption method. Even though we apply our method only to the YAFFS, our method can be easily applied to other NAND flash file systems.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.719-726
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• 2007

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties. However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.

• Journal of Internet of Things and Convergence
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• v.9 no.1
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• pp.71-76
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• 2023

Recently, in order to store and manage big data, research and development of a high-performance storage system capable of stably accessing large data have been actively conducted. In particular, storage systems in data centers and enterprise environments use large amounts of SSD (solid state disk) to manage large amounts of data. In general, SSD uses FTL(flash transfer layer) to hide the characteristics of NAND flash memory, which is a medium, and to efficiently manage data. However, FTL's algorithm has a limitation in using DRAM more to manage the location information of NAND where data is stored as the capacity of SSD increases. Therefore, this paper introduces FTL policies that apply virtual memory to reduce DRAM resources used in FTL. The virtual memory-based FTL policy proposed in this paper manages the map data by using LRU (least recently used) policy to load the mapping information of the recently used data into the DRAM space and store the previously used information in NAND. Finally, through experiments, performance and resource usage consumed during data write processing of virtual memory-based FTL and general FTL are measured and analyzed.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.125-134
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• 2016

NAND flash memory has unique characteristics like as 'out-place-update' and limited lifetime compared with traditional storage systems. According to out-of-place update scheme, a number of invalid (or called dead) pages can be generated. In this case, garbage collection is needed to reclaim invalid pages. Because garbage collection results in not only erase operations but also copy operations of valid (or called live) pages to other blocks, many garbage collection techniques have proposed to reduce the overhead and to increase the lifetime of NAND Flash systems. This techniques sometimes select victim blocks including cold data for the wear leveling. However, most of them overlook the cost of selecting victim blocks including cold data. In this paper, we propose a garbage collection technique named CAPi (Cost Age with Proportion of invalid pages). Considering the additional overhead of what to select victim blocks including cold data, CAPi improves the response time in garbage collection and increase the lifetime in memory systems. Additionally, the proposed scheme also improves the efficiency of garbage collection by separating cold data from hot data in valid pages. In experimental evaluation, we showed that CAPi yields up to, at maximum, 73% improvement in lifetime compared with existing garbage collections.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.77-78
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• 2009

In this paper, we study a pattern-aware write cache policy using a NAND flash memory in disk-based mobile storage systems. Our work is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. Experimental results show that our policy improves the overall I/O performance by reducing the overhead significantly from a non-volatile cache over a traditional one.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.43-50
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• 2016

NAND flash based storage devices adopts multi-channel and multi-way architecture to improve performance using parallel operation of multiple NAND devices. However, multiple NAND devices consume higher current and peak power overlap problem influences on the system stability and data reliability. In this paper, current waveform is measured for erase, program and read operations, peak current and model is defined by profiling method, and estimated probability of peak current overlap among NAND devices. Also, system level TLM simulator is developed to analyze peak overlap phenomenon depending on various simulation scenario. In order to remove peak overlapping, token-ring based simple power management method is applied in the simulation experiments. The optimal peak overlap ratio is proposed to minimize performance degradation based on relationship between peak current overlapping and system performance.