• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Structural Engineering and Mechanics
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• v.26 no.5
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• pp.591-615
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• 2007

An improvement is introduced to solve the plane problems of linear elasticity by reciprocal theorem for orthotropic materials. This method gives an integral equation with complex kernels which will be solved numerically. An artificial boundary is defined to eliminate the singularities and also an algorithm is introduced to calculate multi-valued complex functions which belonged to the kernels of the integral equation. The chosen sample problem is a plate, having a circular or elliptical hole, stretched by the forces parallel to one of the principal directions of the material. Results are compatible with the solutions given by Lekhnitskii for an infinite plane. Five different orthotropic materials are considered. Stress distributions have been calculated inside and on the boundary. There is no boundary layer effect. For comparison, some sample problems are also solved by finite element method and to check the accuracy of the presented method, two sample problems are also solved for infinite plate.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06d
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• pp.82-84
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• 2012

2000년 아이폰의 첫 출시 이후 이동전화를 비롯한 다양한 모바일 단말과 많은 관련 산업이 호황을 누리고 있고 사람들이 컴퓨터를 접하는 시간에 비해 모바일 기기를 접하는 시간 또한 증가하고 있다. 특히 스마트 폰을 통한 웹 트래픽양의 증가량 추이는 기업체들의 PR 수단 변화에 점점 많은 영향을 미치고 있음을 시사하며 특히 기업들이 웹을 통한 홍보 수단인 홈페이지 및 광고 장치들을 스마트 폰 환경에 맞춰야 하는 일이 필요해지고 있다. 본 논문에서 제안하는 모바일 호환 웹 페이지의 자동 생성 프레임워크는 대부분의 웹 브라우저에서 지원하며 다양한 이종 단말환경에서 호환될 수 있는 새로운 웹 표준인 HTML5을 기반으로 한다. 이를 통하여 사용자의 모바일 웹 페이지를 간편하게 생성해주는 프레임워크 및 기반 환경을 제공하여 누구나 손쉽게 모바일 웹 환경에서 이벤트 페이지를 간단히 만들 수 있다. 이는 마치 블로그를 제작할 때 기본 정보를 올리고 템플릿을 선택하는 것처럼 손쉬운 조작을 통해 웹 페이지를 구성할 수 있게 한다.

• Journal of the Korean Institute of Rural Architecture
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• v.14 no.1
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• pp.75-82
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• 2012

Today, educational facilities are considered to be one of the most important built environment. And the appropriate combinations and applications of technical elements related to green building on the education facilities are emphasized and demanded. These are must be compatible with the occupants' activities and their needs. The objective of this research is to identify and analyze of green building technologies, based on Green Educational Facilities' Case Study in Korea, USA, and Japan. As a result of the comparative analysis of this research, the green technological approaches, problem, and characteristics on educational facilities in different area, climate zone are identified and analyzed by external environment, energy, materials and resources, and indoor environment. It is useful as basic reference for future green educational facilities' planning and design in Korea.

• ETRI Journal
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• v.26 no.4
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• pp.307-314
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• 2004

The application of a discrete pseudomorphic high electron mobility transistor (p-HEMT) as a grounded switch allows for the development of low cost phase shifters and phase modulators operating in a Ku band. This fills the gap in the development of phase control devices comprising p-i-n diodes and microwave monolithic integrated circuits (MMICs). This paper describes a discrete p-HEMT characterization and modeling in switching mode as well as the development of a low-cost four-bit phase shifter and direct quadrature phase shift keying (QPSK) modulator. The developed devices operate in a Ku band with parameters comparable to commercially available MMIC counterparts. Both of them are CMOS compatible and have no power consumption. The parameters of the QPSK modulator are very close to the requirements of available standards for satellite earth stations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.59-59
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• 2001

조합회로에 대한 ATPG 알고리듬이 효율적으로 100%의 고장 검출율을 달성할 수 있게 되어 감에 따라서 고장 검출율을 그대로 유지한 상태에서 테스트 패턴을 줄이는 압축 기법의 중요성이 점차로 부각되고 있다. 본 논문에서 제시하는 알고리듬은 고장들간의 독립과 양립 관계에 기초해서, 압축된 테스트 패턴을 위해서는 양립할 수 있는 고장 집합의 크기를 크게 해야 하므로, 고장-패턴 쌍과 고장들간의 독립과 양립 관계를 이용해서 고장-패턴 쌍의 트리 구조를 생성하였다. 이 고장-패턴 트리를 바탕으로 해서 효율적으로 압축된 테스트 패턴을 생성할 수 있었고, ISCAS 85와 ISCAS 89 측정 기준 회로에 대한 결과로 제시된 알고리듬의 우수성을 검증하였다.

• Korean Journal of Computational Design and Engineering
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• v.8 no.4
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• pp.201-211
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• 2003

Collaborative product commerce (CPC) is a newly emerging technology to support inter-enterprise collaboration through the product life-cycle. From the IT point of view, CPC is software technology to integrate product, process and resources of different enterprises using Web technologies. In this paper, we introduce a CPC framework for integrating product information across enterprises, which being developed as a part of the CPC project by ETRI. The product metadata represented by XML schema, which is compatible with ISO STEP PDM Schema standard, is presented to semantically and schematically integrate distributed product information. The web services technologies are discussed to support the interoperability of application systems related to the product development, such as CAD and PDM, where most of these applications run in a distributed environment. Finally, we implement the frame-work to integrate distributed product information.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.17-24
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• 1998

We proposed a novel bondwire inductor buried in plastic package for low cost MMIC and characaterized the electrical perofmrance in a wide frequency range using the full-wave analysis of finite element method(FEM), and then we fabricated and measured the scale-up model in order to prove the characteristics. Th ebondwire inductor has higher quality factor and higher cutoff frequency than the conventional spiral inductor designed n the same area as the bondwire inductor. Since the air-bridge process is not requried for the bondwire inductor, it is very suitable for low cost plastic-packaged MMIC production. The bondwire inductor has the field distribution localized around the bondwire inductor and hence is more compatible to the crosstalk problems.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.