• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.797-804
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• 2013

This paper presents an efficient design method of multiplierless 2-D state space digital filter based on a particle swarm optimization(PSO) algorithm. The design task is reformulated as a constrained minimization problem and is solved by our newly developed PSO algorithm. To ensure the stability of the designed 2-D state space digital filters, a stability strategy is embedded in the basic PSO algorithm. The superiority of the proposed method is demonstrated by several experiments. The results show that the approximation error and roundoff noise of the resultant filters are better than those of the digital filters which designed by recently published filter design methods. In addition, the designed filters with power-of-two coefficients have only about 1/4 computational burden of the 2-D digital filters designed in the 2's complement binary representation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.16-22
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• 1985

In this paper a new algorithm named modified delta modulation (MDM) for encoding filter coefficients is proposed. And this paper presents the designing method of multiplier less FIR filters rosin영 Proposed MDM a19orithm. In the delta modulation (DM) system the quantiaation levels consist of two levels $\pm$1, but in newly proposed MDM algorithm quantization levels are extended to many levels 0, $\pm$2$^n$, n=0, 1, 2... It is recognized by the result of computer simulations that frequency response of multi-plierless FIR filters designed by MDM algorithm is relatively good. And comparing with con-ventional FIR filters on the number of hardware devices, this filter needs a little increased memory, but regardless of filter order it needs only one multiplier which is used for signal scaling.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.577-584
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• 2005

Optimal methods for designing multiplierless minimal complexity FIR filters with cascaded prefilter-equalizer structures are proposed for narrowband communication systems. Assuming that an FIR filter consists of a cyclotomic polynomial(CP) prefilter and an interpolated second order polynomial(ISOP) equalizer, in the proposed method the prefilter and equalizer are simultaneously designed using mixed integer linear programming(MILP). The resulting filter is a cascaded filter with minimal complexity. Design examples demonstrate that the proposed methods produce a more computationally efficient cascaded prefilter-equalizer than other existing filters.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.143-152
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• 2005

Optimal methods for designing multiplierless IIR filters with cascaded prefilter-equalizer structures are proposed for narrowband applications. Assuming that an U filter consists of a cyclotomic Polynomial (CP) prefilter and an all-Pole equalizer based on interpolated first order polynomial (IFOP), in the proposed method the prefilter and equalizer are simultaneously designed using mixed integer linear programming (MILP). The resulting filter is a cascaded filter with minimal complexity. In addition, MtP tries to minimize both computational complexity and phase response non-linearity. Design examples demonstrate that the proposed methods produce a more efficient cascaded prefilter-equalizer than existing methods.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.423-428
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• 2007

Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.65-70
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• 2008

In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.144-154
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• 1999

The binomial sequences are family of orthogonal sequences that can be generated with remarkable simplicity-no multiplications are necessary. This paper introduces a class of non-recursive multidimensional filters for frequency-selective image processing without multiplication operations. The magnitude responses are narrow-band. approximately gaussian-shaped with center frequencies which can be positioned to yield low-pass. band-pass. or high-pass filtering. Algorithms for the efficient implementation of these filters in software or in hardware are described. Also. we show that the binomial QMFs are the maximally flat magnitude square Perfect Reconstruction paraunitary filters with good compression capability and these are shown to be wavelet filters as well. In wavelet transform the original image is decomposed at different scales using a pyramidal algorithm architecture. The decomposition is along the vertical and horizontal direction and maintains constant the number of pixels required to describe the images. An efficient perfect reconstruction binomial QMF-Wavelet signal decomposition structure is proposed. The technique provides a set of filter solutions with very good amplitude responses and band split. The proposed binomial QMF-filter structure is efficient, simple to implement on VLSl. and suitable for multi-resolution signal decomposition and coding applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2249-2254
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• 1994

An observation which is useful for hardware implementation of programmable FIR filters with powers-of two coefficients (2PFIR filters) is made. Specifically, it is shown that the exponents of filter coefficients representable by the canonical signed digit(CSD) code with M ternary digits can be chosen from some subsets of {0, 1, $\cdots$, M-1}. This observation naturally leads to 2PFIR filters with shorter shifters whose length is strictly less than M and, as a consequence, leads to an efficient hardware structure fo programmable 2PFIR filtering. In addition, we present some experimental results indicating that the shifters of 2PFIR filters can be shortened further in some cases.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.