• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.3
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• pp.65-70
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• 2003

In this paper, we propose a scalar multiplication method and its hardware architecture which is resistant to SPA while its computation speed is faster than Colon's. There were SPA-resistant scalar multiplication method which has performance problem. Due to this reason, the research about an efficient SPA-resistant scalar multiplication is one of important topics. The proposed architecture resists to SPA and is faster than Colon's method under the assumption that Colon's and the proposed method use same fmite field arithmetic units(multiplier and inverter). With n-bit scalar multiple, the computation cycle of the proposed is 2n·(Inversion cycle)+3(Aultiplication cycle).

• Journal of the korean Society of Automotive Engineers
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• v.11 no.2
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• pp.24-33
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• 1989

본 고에서는 이러한 추세에 따라서, 보다 효율적인 optimization program에 대해서 소개하고자 한다. 사용한 최적화 알고리즘은 ALM(augmented lagrange multiplier) 방법을 적용해서 구속조건이 있는 문제를 구속조건이 없는 문제로 변환한 후, self-scaling BFGS(broydon-flecher-goldfarb-schanno)를 적용한다. BFGS의 각 descent 방향에서의 step 길이는, sequential search로 unimodal point를 구해서, golden section 방법으로 refine을 한후, cubic approximation을 적용해서 구한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.409-416
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• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• Transactions of the Korean Society of Mechanical Engineers
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• v.15 no.2
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• pp.544-556
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• 1991

The optimization of many engineering design problems requires a nonlinear programming algorithm that is robust and efficient. A general-purpose nonlinear optimization program IDOL (Interactive Design Optimization Library) is developed based on the Augmented Lagrange Mulitiplier (ALM) method. The ideas of selecting a good initial design point, using resonable initial values for Lagrange multipliers, constraints scaling, descent vector restarting, and dynamic stopping criterion are employed for computational enhancement to the ALM method. A descent vector is determined by using the Broydon-Fletcher-Goldfarb-Shanno (BFGS) method. For line search, the Incremental-Search method is first used to find bounds on the solution, then the bounds are reduced by the Golden Section method, and finally a cubic polynomial approximation technique is applied to locate the next design point. Seven typical test problems are solved to show IDOL efficient and robust.

• The Journal of Information Technology
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• v.4 no.3
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• pp.155-163
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• 2001

In this paper, we implemented sigmoid active function which make it difficult to design of the digital neuron networks. Therefore, we designed of the high speed processing of the sigmoid function in order to digital neural networks. we designed of the MAC(Multiplier and Accumulator) operation unit used residue number system without carry propagation for the high speed operation. we designed of MAC operation unit and sigmoid processing unit are proved that it could run of the high speed. On the simulation, the faster than 4.6ns on the each order, we expected that it adapted to the implementation of the high speed digital neural network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the KSME
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• v.21 no.4
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• pp.259-263
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• 1981

본고의 목적은 제한조건이 있는 최소화(constrained minimization) 문제를 해석하는데 있어서 효과적인 방법으로 받아 들여지고있는 Penalty method 에 대한 간단한 개념과 이러한 류의 문제를 해석하는데 이미 사용되어 온 Lagrange multiplier method 와의 연관성, 그리고 이의 유한요소법에의 적용시 고려사항 등에 대하여 간략하게 소개하는데 있다.

• Journal of the Korean Geographical Society
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• v.40
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• pp.55-71
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• 1989

이 글에서는 다음의 내용을 다루었다. 1. 연구지역 및 방법 2. 소득승수효과의 공간적 특색 3. 공간경제정책과 승수효과

• The Journal of the Acoustical Society of Korea
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• v.3 no.2
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• pp.30-34
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• 1984

본 논문에서는 인코히어런트광 매트릭스-벡터곱셈기를 이용하여 입력 데이터를 광학적으로 DFT 할 수 있는 방법을 연구하였다. DFT의 웨이팅함수를 매트릭스로 나타내어 본 논문에서 제시한 2 개의 성분 분할 방법을 이용하여 마스크상에 부호화하고 광매트릭스-벡터곱셈기내에 고정시켜서 입력 데이터와 광학적으로 곱하도록 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1403-1408
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• 2021

Recently, FPGA-based AI processors are being studied actively. Deep convolutional neural networks (CNN) are basic computational structures performed by AI processors and require a very large amount of multiplication. Considering that the multiplication coefficients used in CNN inference operation are all constants and that an FPGA is easy to design a multiplier tailored to a specific coefficient, this paper proposes a methodology to optimize the multiplier. The method utilizes 2's complement and distributive law to minimize the number of bits with a value of 1 in a multiplication coefficient, and thereby reduces the number of required stacked adders. As a result of applying this method to the actual example of implementing CNN in FPGA, the logic usage is reduced by up to 30.2% and the propagation delay is also reduced by up to 22%. Even when implemented with an ASIC chip, the hardware area is reduced by up to 35% and the delay is reduced by up to 19.2%.