• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.298-305
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• 2004

This paper presents an error compensation method for a fixed-width modified Booth multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50％ by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 40％ reduction in area and power consumption of a multiplier compared with the ideal multiplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.347-356
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• 2003

The OCT algorithm needs efficient hardware architecture to compute inner product. The conventional methods have large hardware complexity. Because of this reason. a computation sharing multiplier was proposed for implementing inner product. However, the existing multiplier has inefficient hardware architecture in precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we proposed a new efficient computation sharing multiplier and applied it to implementation of 1-D DCT processor. The comparison results show that the new multiplier is more efficient than an old one when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using the proposed multiplier is more high performance than typical design methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.391-396
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• 2010

This paper presents some important research result comparisons for multi function RF modules which use amplifier or frequency multiplier. By using multiplier, multi function module can be realized amply in comparison to multi band module which has separate block for each frequency band. Some com paring analysis among the switching method between separate amplifier and multiplier, the structure using frequency selective reflector, and the module using the defected ground structure. The multi function module which operates as amplifier or multiplier with input frequency is developed and input frequency suppression and output harmonics suppression can be improve d by using defected ground structure.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.115-121
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• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

• Proceedings of the Korean Geotechical Society Conference
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• 2000.11a
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• pp.253-260
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• 2000

Pile foundations have been widely used in civil engineering construction for many years. Structures subjected to large lateral loads usually have pile foundations as shallow foundations cannot sometimes support the moments on these structure. The purpose of this paper is to propose the p - multiplier factor (P$\sub$M/) based on the characteristics of behavior of laterally loaded group pile in homogeneous sand. For this, a series of model tests are performed and the composite analytical method proposed by author is used to the propose P$\sub$M/. Based on the model test results of the large number of laterally loaded group piles, p - multiplier factors for homogeneous sand are proposed by back analysis under various condition of soil density, spacing-to-diameter ratio of pile, number of pile, and spacing-to-diameter of pile. P - multiplier approach provides a simple but sufficient tool for characterizing the shadowing group effects of laterally loaded group pile.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.33-40
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• 2004

The divide-and-conquer method is efficiently used in parallel multiplier over finite field $GF(2^n)$. Leone Proposed optimal stop condition for iteration of Karatsuba-Ofman algerian(KOA). Ernst et al. suggested Multi-Segment Karatsuba(MSK) method. In this paper, we analyze the complexity of a parallel MSK multiplier based on the method. We propose a new parallel MSK multiplier whose space complexity is same to each other. Additionally, we propose optimal stop condition for iteration of the new MSK method. In some finite fields, our proposed multiplier is more efficient than the KOA.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.33-44
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• 2008

The efficiency of pairing based cryptosystems depends on the computation of pairings. pairings is defined over finite fileds GF$(3^m)$ by trinomials due to efficiency. The hardware architectures for pairings have been widely studied. This paper proposes new adder and multiplier for GF(3) which are more efficient than previous results. Furthermore, this paper proposes a new unified adder-subtractor for GF$(3^m)$ based on the proposed adder and multiplier. Finally, this paper proposes new multiplier for GF$(3^m)$. The proposed MSB-first bit-serial multiplier for GF$(p^m)$ reduces the time delay by approximately 30 % and the size of register by half than previous LSB-first multipliers. The proposed multiplier can be applied to all finite fields defined by trinomials.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.846-853
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• 2009

This paper presents the design of a high efficiency frequency multiplier with load-pull simulation and analyses the nonlinear distortion of the frequency multiplier. The frequency multiplier shows serious distortion of multiplying signal bandwidth because of nonlinearity when modulated signal is applied, so a digital predistortion with look up table (LUT) is applied to compensate for the distortion of the frequency multiplier. The frequency multiplier is designed to produce 5.8GHz output by doubling the input frequency to be operating at IEEE 802.11a standard wireless LAN. The output spectrum shows 12dB ACPR improvement both at +11MHz, +20MHz offset from center frequency after linearization.