• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.379-385
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• 2015

This paper proposes the hardware architecture of high performance ALF(Adaptive Loop Filter) for efficient filter coefficient estimation. In order to make the original image which has high resolution and high quality into highly compressed image effectively and also, subjective image quality into improved image, the ALF technique of HEVC performs a filtering by estimating filter coefficients using statistical characteristics of image. The proposed ALF hardware architecture is designed with a 2-step pipelined architecture for a reduction in performance cycle by analysing an operation relationship of Cholesky decomposition for the filter coefficient estimation. Also, in the operation process of the Cholesky decomposition, a square root operation is designed to reduce logic area, computation time and computation complexity by using the multiplexer, subtracter and comparator. The proposed hardware architecture is designed using Xilinx ISE 14.3 Vertex-7 XC7VCX485T FPGA device and can support 4K UHD@40fps in real time at a maximum operation frequency of 186MHz.

• Journal of the Optical Society of Korea
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• v.18 no.3
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• pp.261-273
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• 2014

In this paper, metal insulator metal (MIM) plasmonic slot cavity narrow band-pass filters (NBPFs) are studied. The metal and dielectric of the structures are silver (Ag) and air, respectively. To improve the quality factor and attenuation range, two novel NBPFs based on tapered structures and double cavity systems are proposed and numerically analyzed by using the two-dimensional (2-D) finite difference time domain (FDTD) method. The impact of different parameters on the transmission spectrum is scrutinized. We have shown that increasing the cavities' lengths increases the resonance wavelength in a linear relationship, and also increases the quality factor, and simultaneously the attenuation of the wave transmitted through the cavities. Furthermore, increasing the slope of tapers of the input and output waveguides decreases attenuation of the wave transmitted through the waveguide, but simultaneously decreases the quality factor, hence there should be a trade-off between loss and quality factor. However, the idea of adding tapers to the waveguides' discontinuities of the simple structure helps us to improve the device total performance, such as quality factor for the single cavity and attenuation range for the double cavity. According to the proposed NBPFs, two, three, and four-port power splitters functioning at 1320 nm and novel ultra-compact two-wavelength and triple-wavelength demultiplexers in the range of 1300-1550 nm are proposed and the impacts of different parameters on their performances are numerically investigated. The idea of using tapered waveguides at the structure discontinuities facilitates the design of ultra-compact demultiplexers and splitters.

• Journal of Advanced Navigation Technology
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• v.22 no.2
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• pp.57-63
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• 2018

In the case of aircraft-launched guided weapons, various interface tests such as MIL-STD-1760 based power source, discrete signal, MUX communication as well as BIT of missile can verify system safety and reliability. The purpose of this case study is to develop a test bench based on MIL-STD-1760E for interoperability testing between aircraft and weapons. We proposed a testing method of the launch sequence based on the defined TIME LINE in the development phase of the missile system from the application of the power of the missile to the targeting, the transfer order, and the missile separation process. Furthermore, it will be a reference model that can maximize the verification scope in the development phase of the air to surface missile system by simulating abnormal situation to the inert missile using the error insertion function.

• Nuclear Engineering and Technology
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• v.55 no.10
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• pp.3822-3830
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• 2023

The large-area Compton camera (LACC), featuring significantly high detection sensitivity, was developed for high-speed localization of gamma-ray sources. Due to the high gamma-ray interaction event rate induced by the high sensitivity, however, the multiplexer-based data acquisition system (DAQ) rapidly saturated, leading to deteriorated energy and imaging resolution at event rates higher than 4.7 × 10³ s^-1. In the present study, a new simultaneous multi-channel DAQ was developed to improve the energy and imaging resolution of the LACC even under high event rate conditions (10⁴-10⁶ s^-1). The performance of the DAQ was evaluated with several point sources under different event rate conditions. The results indicated that the new DAQ offers significantly better performance than the existing DAQ over the entire energy and event rate ranges. Especially, the new DAQ showed high energy resolution under very high event rate conditions, i.e., 6.9% and 8.6% (for 662 keV) at 1.3 × 10⁵ and 1.2 × 10⁶ s^-1, respectively. Furthermore, the new DAQ successfully acquired Compton images under those event rates, i.e., imaging resolutions of 13.8° and 19.3° at 8.7 × 10⁴ and 10⁶ s^-1, which correspond to 1.8 and 73 μSv/hr or about 18 and 730 times the background level, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.36-45
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• 1999

In order to control the flow of traffics in ATM networks and optimize the usage of network resources, an efficient control mechanism is necessary to cope with congestion and prevent the degradation of network performance caused by congestion. In this paper, Buffered Leaky Bucket which applies the same control scheme to a variety of traffics requiring the different QoS(Quality of Service) and Neural Networks lead to the effective buffer utilization and QoS enhancement in aspects of cell loss rate and mean transfer delay. And the cell scheduling algorithms such as DWRR and DWEDF for multiplexing the incoming traffics are enhanced to get the better fair delay. The network congestion information from cell scheduler is used to control the predicted traffic loss rate of Neural Leaky Bucket, and token generation rate and buffer threshold are changed by the predicted values. The prediction of traffic loss rate by neural networks can enhance efficiency in controlling the cell loss rate and cell transfer delay of next incoming cells and also be applied for other traffic controlling schemes. Computer simulation results performed for random cell generation and traffic prediction show that QoSs of the various kinds of traffcis are increased.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.15-26
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• 2005

In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

• Journal of Animal Science and Technology
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• v.47 no.4
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• pp.691-696
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• 2005

Suckling piglets must avoid positions with high air velocity because they don’t have hypodermic fat. Therefore this study examined the effects of air ejection on the behaviors of sows and their piglets. Compressed air was released for 5s at 5s intervals between floor and udder of sows only when they were standing or sitting. Sixteen multiparous crossbred(Landrace×Yorkshire) sows and their piglets were used. Behaviors of sixteen sows and their piglets were recorded for 4 days postpartum, using the LED lamp(wavelength:950nm), CCD camera(Samsung SDC-411), multiplexer(Samsung SDM-080), and time lapsed VCR(Samsung SRV-30). The videotapes were scanned every 30s to obtain an instantaneous behavioral sample. The sow’s standing and sitting rates between control group(CG) and air ejection group(AEG) were not significantly different(P＞0.05). This means that air ejection does not affect the behavior of sows. Frequency of the suckling piglets’ behaviors closely related to the crushing by sows was lower in AEG than in CG(P＜0.05). These results suggest that air ejection may be available for reduction of the crushing of suckling piglets by sows.

• Korean Journal of Veterinary Research
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• v.45 no.2
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• pp.245-250
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• 2005

This study was carried out to find out how space allowance affect the social behavior of Korean native cattle (Bos taurus coreanae) steers. Twelve Korean native cattle (Bos taurus coreanae) steers were used as subjects, each of which was 30-month-old and observation period was from June to July 2003. Five (T1) and seven (T2) steers were allotted to two pens of $5m{\times}10m$ in a building with slate roof and open sides respectively. They were fed at 09:00 h and 16:00 h, twice a day. The behaviors of steers were recorded from 06:00 h to 17:00 h, using two color CCD cameras (Samsung SDC-411, Korea), one B/W CCD cameras (Samsung SBC-340, Korea), one multiplexer (Samsung SDM-081, Korea) and a time lapse VCR (Samsung SRV-30, Korea). The behaviors of each steer were recorded every 2 min using an instantaneous point sampling method. While the mean percentage of time budget in WA of T1 was lower than that of T2 (p<0.05), the mean percentage of time budget in SF of T1 was higher than that of T2 (p<0.05). When it gets hot, steers in T1 rested from 10:00 h to 14:00 h when it gets cool, showing 40~80% of LD rate while steers in T2 rested from 12:00 h, when it very hot to 17:00 h, showing 20~50% of LD rate, which is relatively low. Steers in T1 were fed from 06:00 h to 08:00 h when it was cool and from 16:00 h to 18:00 h, showing 20~45% of EA rate while steers in T2 were fed from 08:00 h to 14:00 h when it was hot, showing 25~50% of EA rate. In conclusion, it turned out that the number of steers affected their social behavior, and T1 was better environment than T2 in terms of welfare.