• Journal of Communications and Networks
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• v.6 no.2
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• pp.93-105
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• 2004

This paper discusses cyclostationary interference suppression for multiuser wired communication systems. Crosstalk interference from digital signals in multipair cables has been shown to be cyclostationary. Many crosstalk equalization or suppression techniques have been proposed which make implicit use of the cyclostationarity of the crosstalk interferer. In this paper, the convergence and steady-state behaviors of a fractionally spaced equalizer (FSE) in the presence of multiple cyclostationary crosstalk interference are thoroughly analyzed by using the equalizer's eigenstructure. The eigenvalues with multiple cyclostationary interference depend upon the folded signal and interferer power spectra, the cross power spectrum between the signal and the interferer, and tile cross power spectrum between the interferers, which results in significantly different initial convergence and steady-state behaviors as compared to the stationary noise case. The performance of the equalizer varies depending on the relative clock phase of the symbol clocks used by the signal and multiple interferers. Measued characteristics as well as analytical model of NEXT/FEXT channel are used to compute the optimum and worst relative clock phases among the signal and multiple interferers.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.06a
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• pp.75-81
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• 1997

A new DTPP (Desk-Top Program Production) system has been developed that enables multiple program producers (directors) working at different locations to collaborate over a computer network and prepare a single program for broadcasting. In this system, information is shared among users by exchanging data edited on non-linear editing terminals in program post-production work over a network in real time. In short, the new DTPP system provides a collaborative work space for producing TV programs. The system does not make use of a special server for collaborative work but rather multiple interconnected editing terminals having the same functions. In this configuration, data at a terminal which has just been edited by some operation is forwarded to all other connected terminals for updating. This form of information sharing, however, requires that some sort of data synchronizing method be established since multiple terminals are operating on the same data simultaneously. We therefore adopt a method whereby the system synchronizes the clocks on each terminal at the time of connection and sends an operation time stamp together with edited data. This enables most recently modified data to be identified and all information on all terminals to be updated appropriately. This paper provides an overview of this new collaborative DTPP system and describes the techniques for exchanging edited data and synchronizing data.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.773-779
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• 2013

We propose an efficient method to measure a pulse width using multiphase clock signals generated from a ring oscillator. These clocks, which have the same frequency and are evenly spaced, give multiple rising edges within a clock cycle. Thus, it is possible to measure a pulse width more accurately than with existing single clock-based methods. The proposed method is applied to a capacitive touch switch. Experimental results show that the capacitive touch switch with the proposed method gives a 118 fF resolution, which is 6.4 times higher than that of the touch switch with a single clock-based pulse width measurement method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1241-1249
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• 2011

There are TOA, TDOA and AOA method to estimate the position of the electromagnetic wave transmitter by using the multiple receivers at the fixed position. Among these methods, AOA method is suitable for the jammer localization system. Because TOA method can be adopted for the clocks of the transmitter and the receiver are synchronized each other, and TDOA method can be only adopted for a broad-band jamming signal. This paper, therefore, analyzes the characteristics of the AOA measurements and the sensitivity of the positioning performance according to the system design parameters. Based on the analyzed results, the jammer localization system to meet the desired performance is designed, and it has been checked that the positioning error for the jammer located at a distance of 10km is lower than 38m through the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of Positioning, Navigation, and Timing
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• v.12 no.3
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• pp.245-255
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• 2023

Time comparison techniques are necessary for generating and keeping Coordinated Universal Time (UTC) and distributing standard time clocks. Global Navigation Satellite System (GNSS) Common View, GNSS All-in-View, Two-Way Satellite Time and Frequency Transfer (TWSTFT), Very Long Baseline Interferometry (VLBI), optical fiber, and Network Time Protocol (NTP) based methods have been used for time comparison. In these methods, GNSS based time comparison techniques are widely used for time synchronization in critical national infrastructures and in common areas of application such as finance, military, and wireless communication. However, GNSS-based time comparison techniques are vulnerable to jamming or interference environments and it is difficult to respond to GNSS signal disconnection according to the international situation. In response, in this paper, Code-Division Multiple Access (CDMA) based All-to-All TWSTFT operation method is proposed. A software-based simulation platform also was designed for performance analysis in multi-TWSTFT signal environments. Furthermore, code and carrier measurement jitters were calculated in multi-signal environments using the designed simulation platform. By using the technique proposed in this paper, it is anticipated that the TWSTFT-based time comparison method will be used in various fields and satisfy high-performance requirements such as those of a GNSS master station and power plant network reference station.