• Journal of Power Electronics
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• 제14권2호
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• pp.282-291
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• 2014

This paper presents a detailed theoretical analysis and performance assessment of the capacitor voltage balancing strategies for staircase modulated modular multilevel converters (MMC) in terms of the algorithm structures, voltage balancing effect, and switching frequency. A constant-frequency redundancy selection (CFRS) method with minimal switching loss is proposed and the function realization of specific modules of the algorithm is given. This method is simple and efficient in both switching frequency and regulation capacity. Laboratory results show very good agreement with the theoretical analysis and numerical simulations.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• Journal of Power Electronics
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• 제10권4호
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• pp.357-364
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• 2010

In this paper, a novel analysis of a carrier based PWM method for multilevel inverters is presented. The space vector PWM and carrier based PWM correlations in multilevel inverters are investigated in a nominal two-level switching diagram. The obtained results can be applied to design various carrier PWM techniques. In this paper, a carrier based single-state PWM technique, which reduces the switching number and optimizes the active voltage errors, is presented. This PWM technique can be advantageous if there are a large number of levels. The proposed method is mathematically formulated and demonstrated by simulations and experimental results.

• 전력전자학회논문지
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• 제20권5호
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• pp.448-455
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• 2015

A model predictive control (MPC) method without individual PWM has been recently researched to simplify and improve the control flexibility of a multilevel inverter. However, the input power of each H-bridge cell and the switching frequency of switching devices are unbalanced because of the use of a restricted switching state in the MPC method. This paper proposes a control method for balancing the switching patterns and cell power supplied from each isolated dc source of a cascaded H-bridge inverter. The supplied dc power from isolated dc sources of each H-bridge cells is balanced with the proposed cell balancing method. In addition, the switching frequency of each switching device of the CHB inverter becomes equal. A simulation and experimental results are presented with nine-level and five-level three-phase CHB inverter to validate the proposed balancing method.

• 전력전자학회논문지
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• 제22권6호
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• pp.476-483
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• 2017

In this paper, a voltage-based model predictive control (MPC) scheme for a modular multilevel converter is used to reduce switching loss. The proposed method calculates an offset voltage that clamps the switching operation of submodules in which the current greatly flows at every sampling period by using the reference phase voltage and the reference phase current. To use the offset voltage, the proposed method converts the current-based MPC to the voltage-based MPC. The proposed voltage-based MPC then generates a new reference pole voltage that clamps the switching of submodules by applying the calculated offset voltage to the phase voltage. Therefore, the proposed method can reduce the switching loss by stopping the switching operation of submodules in which the current greatly flows. The switching loss reduction effect of the proposed method is verified by comparing its loss data with those of the conventional MPC method.

• Journal of Power Electronics
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• 제17권1호
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• pp.115-126
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• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

• Journal of Power Electronics
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• 제16권2호
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• pp.490-497
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• 2016

The analysis of the switch status of each unit module of a cascaded multi-level inverter reveals that the working condition of the switch of a chopper arm causes unnecessary switching under the conventional unipolar sinusoidal pulse width modulation (SPWM). With an increase in the number of cascaded multilevel inverters, the superposition of unnecessary switching gradually occurs. In this work, we propose an improved SPWM strategy to reduce switching in cascaded multilevel inverters. Specifically, we analyze the switch state of the switch tube of a chopper arm of an H-bridge unit. The redundant switch is then removed, thereby reducing the switching frequency. Unlike the conventional unipolar SPWM technique, the improved SPWM method greatly reduces switching without altering the output quality of inverters. The conventional unipolar SPWM technique and the proposed method are applied to a five-level inverter. Simulation results show the superiority of the proposed strategy. Finally, a prototype is built in the laboratory. Experimental results verify the correctness of the proposed modulation strategy.

• Journal of Power Electronics
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• 제12권4호
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• Journal of Power Electronics
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• 제16권1호
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• pp.340-350
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• 2016

A cascaded hybrid multilevel inverter including a reconfiguration technique for low voltage dc distribution applications is proposed in this paper. A PWM generation fault detection and reconfiguration paradigm after an inverter cell fault are developed by using only a single-chip controller. The proposed PWM technique is also modified to reduce switching losses. In addition, the proposed topology can reduce the number of required power switches compared to the conventional cascaded multilevel inverter. The proposed technique is validated by using a 3-kVA prototype. The switching losses of the proposed multilevel inverter are also investigated. The experimental results show that the proposed hybrid inverter can improve system efficiency, reliability and cost effectiveness. The efficiency of proposed system is 97.45% under the tested conditions. The proposed hybrid inverter topology is a promising method for low voltage dc distribution and can be applied for the multiple loads which are required in a data center or telecommunication building.

• Journal of Power Electronics
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• 제19권1호
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• pp.244-253
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• 2019

Finite control set model-predictive control (FCS-MPC) has received increasing attentions due to its outstanding dynamic performance. It is being widely used in power converters and multilevel inverters. However, FCS-MPC requires a lot of calculations, especially for multilevel-cascaded H-bridge (CHB) static synchronous compensators (STATCOMs), since it has to take account of all the feasible voltage vectors of inverters. Hence, an improved five-segment space vector pulse width modulation (SVPWM) method based on the non-orthogonal static reference frames is proposed. The proposed SVPWM method has a lower number of switching states and requires fewer computations than the conventional method. As a result, it makes FCS-MPC more efficient for multilevel cascaded H-bridge STATCOMs. The partial cost function is adopted to sequentially solve for the reference current and capacitor voltage. The proposed FCS-MPC method can reduce the calculation burden of the FCS-MPC strategy, and reduce both the switching frequency and power losses. Simulation and experimental results validate the excellent performance of the proposed method when compared with the conventional approach.