• 한국광학회지
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• 제31권4호
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• pp.169-175
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• 2020

격자의 구조가 간단하고 격자의 대조비가 낮은 SBC 시스템 구성을 위한 무편광 유전체 다층박막 회절격자를 설계하였다. SBC 방법으로 결합한 빔의 빔 품질을 높게 유지하기 위하여 회절격자의 파면 왜곡이 최소화되는 구조를 제안하였으며, 오염에 의한 흡수가 발생하지 않고 회절격자를 제작할 수 있는 구조로 회절격자를 최적화 설계하였다. 설계된 회절격자는 1055 nm 중심파장에서 Littrow 각도로 입사하는 경우 무편광 -1차 회절 효율이 99.36%이었으며, 96% 이상의 무편광 회절 효율을 나타내는 공정 여분이 확보되어 있음을 확인하였다.

• 한국진공학회지
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• 제17권2호
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• pp.113-116
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• 2008

반도체 소자 집적도의 비약적인 발전으로 인하여 반도체 공정은 더욱 다층화 되어가고 있다. 이러한 다층화 공정에서는 필수적으로 여러 단계의 패턴을 형성하기 위하여 Photoresist(PR)를 이용한 식각 공정을 사용하게 된다. 이러한 식각 공정에서 다단계 식각 공정으로 인한 공정시간 증가와 식각 후 남은 잔여 PR residue는 초고집적화된 현 반도체 산업에서는 소자에 치명적인 문제를 발생시킨다. 따라서 본 연구에서는 기존 PR strip 용액을 플라즈마에 의하여 액체 상태로 활성화하여 기존의 건식세정법과 습식세정법을 동시에 사용하여 PR을 효과적으로 제거하기 위한 방법을 연구하였다. 플라즈마에 의하여 약액을 활성화하기 위하여 먼저 플라즈마 약액활성화를 위한 장치를 simulation하여 실험 장치에서 균일한 gas흐름을 확인하였다. 이후 플라즈마의 세기를 0V에서 100V까지 증가시켜 약액을 활성화한 후 PR을 strip하여 각 플라즈마 세기에서의 식각률을 조사하였으며 80V에서 가장 빠른 식각률을 나타났다. 또한 0V와 80V의 Dilution에 대한 영향을 확인하였으며 약액을 Dilution 후에도 식각률은 더욱 향상됨을 확인할 수 있었다. 이러한 세정 시간의 단축은 여러 단계의 식각 공정 시간을 단축하여 반도체 공정에서 소자 생산을 위한 시간을 단축하게 된다. 또한 각 세정공정마다 증가한 세정 공정으로 인하여 세정액의 사용이 많아져 세정액 폐수로 인한 환경문제가 심각해지고 있다. 세정 약액 활성화 방법을 사용함으로써 세정액의 절감효과가 나타난다.

• 한국유변학회:학술대회논문집
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• 한국유변학회 2002년도 추계학술발표회 논문집
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• pp.51-54
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• 2002

No Abstract, See Full Text

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 춘계학술대회 논문집
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• pp.92-92
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• 2009

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.212-213
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• 2005

In this study, in order to develop low temperature sintering piezoelectric actuator, $Pb_{0.985}Bi_{0.01}(Mg_{1/2}W_{1/2})_{0.03}(Ni_{1/3}Nb_{2/3})_{0.13}(Zr_{0.50},Ti_{0.50})_{0.84}$ (PMW-PNN-PZT) ceramic systems were fabricated using $CaCO_3-Li_2CO_3$, sintering aid through a post-annealing process. The sinterability of PMW-PNN-PZT ceranics was remarkably enhanced by liquid phase sintering of $CaCO_3$ and $Li_2CO_3$. But, it was confimed form the X-ray diffraction pattern that the secondary phase along grain boundaries, deteriorated the piezoelectric properties. The secondary phase along grain boundaries was significantly removed by annealing after sintering. The 0.2wt% $Li_2CO_3$-0.25wt% $CaCO_3$-added PMW-PNN-PZT ceramics post-annealed at 900$^{\circ}C$ for 90min exhibited the excellent electromechanical coupling factor($k_p$) of 63.3% and piezoelectric constant($d_{33}$) of 452pC/N, respectively, for multilayer piezoelectricactuatorapplication.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.549-550
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• 2006

It has become topic continuously at MEMS or semiconductor process to form three-dimensional multilayer structure. In this paper, we devised the new polymer pattern method that has multilayer structure. This is method that uses different kind of polymeric material. Specially, polymers used in this study that we propose became all pattern by photolithography, prevented that process increases. Here, polymer that we use used polymer of epoxy order called "SU-8" and polymer of novolak resin called "AZ-1518". The result, "SU-8" was formed pattern to 3.5um thickness, and "AZ-1518" about pattern 3um thickness. Also, It was been 6um thickness at same pattern area.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.43-50
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• 2021

The properties of materials which are widely used in industry fields like automobile, shipbuilding, casting, and electronics are strongly needed to have higher surface hardness, lower surface roughness, and higher compressive residual stress. As mentioned above, for the purpose of satisfying three factors, a variety of researches with respect to surface improvement have been actively studied and applied to every industry. SKD61 which is mostly used for die casting process of cold chamber method must meet a countless number of problems which are thermal, mechanical and chemical from highly specific working environment at high temperature over 600℃. Above all, in case of plunger sleeves used for die casting process, thermal fatigue has a bad effect on the surface of an inlet where molten metal is repeatedly injected. On account of it, plunger sleeves cause manufacturers to deteriorate quality of products. Therefore, in this paper, to improve the surface of an inlet of plunger sleeve, multilayer PVD coating using Ti, Cr and Mo is suggested. Furthermore, The surface characteristics such as surface roughness(Rsa, Rsq), surface hardness(HRB, HRC) and residual stress using XRD(X-ray diffractometer) of coated samples and specimens are studied and discussed.

• 한국환경과학회지
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• 제15권2호
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• pp.141-155
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• 2006

This study is aimed at the development of a runoff forecasting model to solve the uncertainties occurring in the process of rainfall-runoff modeling and improve the modeling accuracy of the stream runoff forecasting, The study area is the downstream of Naeseung-chun. Therefore, time-dependent data was obtained from the Wolpo water level gauging station. 11 and 2 out of total 13 flood events were selected for the training and testing set of model. The model performance was improved as the measuring time interval$(T_m)$ was smaller than the sampling time interval$(T_s)$. The Neuro-Fuzzy(NF) and TANK models can give more accurate runoff forecasts up to 4 hours ahead than the Feed Forward Multilayer Neural Network(FFNN) model in standard above the Determination coefficient$(R^2)$ 0.7.

• 통합자연과학논문집
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• 제2권1호
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• pp.13-17
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• 2009

A newly developed OTFT manufacturing process using the combination of self-assembly techniques and vapor phase polymerization method revealed that a thick $SiO_2$ dielectric layer (100~200 nm) is not well compatible with conducting polymer electrode, thereby resulting in still recognizable contact resistance, unstable $V_{th}$ and leaking off current. A couple of very recent studies showed that this issue may be solved by replacing such inorganic dielectric with a self-assembled monolayer or multilayer (organic) dielectric. Therefore, this short review introduces recent trends in the development of high performance thin film transistor consisting of both organic semiconductor and SAM dielectric.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.11-15
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• 2002

3 V, 2.46GHz Low Noise Amplifier (LNA) have been designed for standard 0.35$\mu\textrm{m}$ CMOS process with one poly and four metal layers. This design includes on-chip biasing, matching network and multilayer spiral inductors. The single-ended amplifier provides a forward gain of 20.5dB with a noise figure 3.35dB, and an IIP3 of -6dBm while drawing 59mW total Power consumption