• Journal of Korea Water Resources Association
• /
• v.53 no.6
• /
• pp.395-408
• /
• 2020

This paper aims to develop and apply three different machine learning approaches (i.e., artificial neural networks (ANN), adaptive neuro-fuzzy inference systems (ANFIS), and wavelet-based neural networks (WNN)) combined with an evolutionary optimization algorithm and the k-fold cross validation for multi-step (days) streamflow forecasting at the catchment located in Algeria, North Africa. The ANN and ANFIS models yielded similar performances, based on four different statistical indices (i.e., root mean squared error (RMSE), Nash-Sutcliffe efficiency (NSE), correlation coefficient (R), and peak flow criteria (PFC)) for training and testing phases. The values of RMSE and PFC for the WNN model (e.g., RMSE = 8.590 ㎥/sec, PFC = 0.252 for (t+1) day, testing phase) were lower than those of ANN (e.g., RMSE = 19.120 ㎥/sec, PFC = 0.446 for (t+1) day, testing phase) and ANFIS (e.g., RMSE = 18.520 ㎥/sec, PFC = 0.444 for (t+1) day, testing phase) models, while the values of NSE and R for WNN model were higher than those of ANNs and ANFIS models. Therefore, the new approach can be a robust tool for multi-step (days) streamflow forecasting in the Seybous River, Algeria.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.2
• /
• pp.174-182
• /
• 2002

The object-oriented design methods and their CASE tools are widely used in practice by many real-time software developers. However, object-oriented CASE tools require an additional step of identifying tasks from a given design model. Unfortunately, it is difficult to automate this step for a couple of reasons: (1) there are inherent discrepancies between objects and tasks; and (2) it is hard to derive tasks while maximizing real-time schedulability since this problem makes a non-trivial optimization problem. As a result, in practical object-oriented CASE tools, task identification is usually performed in an ad-hoc manner using hints provided by human designers. In this paper, we present a systematic, schedulability-aware approach that can help mapping real-time object-oriented models to multi-threaded implementations. In our approach, a task contains a group of mutually exclusive transactions that may possess different periods and deadline. For this new task model, we provide a new schedulability analysis algorithm. We also show how the run-time system is implemented and how executable code is generated in our frame work. We have performed a case study. It shows the difficulty of task derivation problem and the utility of the automated synthesis of implementations as well as the Inappropriateness of the single-threaded implementations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.31 no.2
• /
• pp.117-121
• /
• 2018

Perovskite solar cells have received increasing attention in recent years because of their outstanding power conversion efficiency (exceeding 22%). However, they typically contain toxic Pb, which is a limiting factor for industrialization. We focused on preparing Pb-free perovskite films of Ag-Bi-I trivalent compounds. Perovskite thin films with improved optical properties were obtained by applying an anti-solvent (toluene) washing technique during the spin coating of perovskites. In addition, the surface condition of the perovskite film was optimized using a multi-step thermal annealing treatment. Using the optimized process parameters, $AgBi_2I_7$ perovskite films with good absorption and improved planar surface topography (root mean square roughness decreased from 80 to 26 nm) were obtained. This study is expected to open up new possibilities for the development of high performance $AgBi_2I_7$ perovskite solar cells for applications in Pb-free energy conversion devices.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.14 no.8
• /
• pp.757-766
• /
• 2004

This paper focuses on the formulation and validation of an automatic strategy to select the optimal location and direction of strain gauges for the measurement of the modal response. These locations and directions are important to render the strain measurements as robust as possible when a random mispositioning of the gauges and gauge failures are expected. The approach relies on the evaluation of the signal-to-noise ratios of the gauge measurements from strain data of finite element. The multi-step optimization strategy including genetic algorithm is used to find the strain gauge locations-directions that maximize the smallest modal strain signal-to-noise ratio in the absence of gauge failure or its expected value when gauge failure is possible. A flat Plate is used to prove the applicability of the proposed methodology and to demonstrate the effects of the essential parameters of the problem such as the mispositioning level, the probability of gauge failure, and the number of gauges.

• Journal of the Society of Naval Architects of Korea
• /
• v.45 no.3
• /
• pp.303-308
• /
• 2008

The induction heating is more efficient for a plate bending because of its easy operation and control of working parameters, compared with the heating by a gas torch. The existing axis symmetric analysis method could neither handle initial curved plates nor be used in the optimization of coil shapes because of its limit of an axis symmetric coil shape. But the proposed method using some discrete part models and analysis processes could overcome these difficulties and show more accurate results in temperatures and deflections of flat or curved plates with initial curvature than those in the existing axis symmetric analysis method. This method is composed of the multi-disciplinary analyses such as an electro magnetic analysis, a heat transfer analysis and a deformation analysis based on inherent strain approach per each step. Traditionally, the coil shape in the induction heating is circular shape and it needs the moving process along heating lines. To overcome this, the 'Long Type Coil' with some linear parallel coils was proposed. It did not need the moving process along heating lines and reduced the heating process time. The results of experiments were compared with those of the simulation.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.12
• /
• pp.1539-1547
• /
• 1999

캐리-세이브 가산기 (CSA)는 회로 설계 과정에서 빠른 연산 수행을 위해 가장 널리 이용되는 연산기 중의 하나이다. 그러나, 현재까지 산업체에서 CSA를 이용한 설계는 설계자의 경험에 따른 수작업에 의존하고 있고 그 결과 최적의 회로를 만들기 위해 매우 많은 시간과 노력이 소비되고 있다. 이에 따라 최근 CSA를 기초로 하는 회로 합성 자동화 기법에 대한 연구의 필요성이 대두되고 있는 상황에서, 본 논문은 연산 속도를 최적화하는 효율적인 CSA 할당 알고리즘을 제안한다. 우리는 CSA 할당 문제를 2단계로 접근한다: (1) 연산식의 멀티 비트 입력들만을 고려하여 최소 수행 속도 (optimal-delay)의 CSA 트리를 할당한다; (2) (1)에서 구한 CSA 트리의 수행 속도 증가가 최소화 (minimal increase of delay) 되는 방향으로 CSA들의 캐리 입력 포트들에 나머지 싱글 비트 입력들을 배정한다. 실제 실험에서 우리의 제안된 알고리즘을 적용하여 연산식들의 회로 속도를 회로 면적의 증가 없이 상당한 수준까지 줄일 수 있었다.Abstract Carry-save-adder (CSA) is one of the most widely used implementations for fast arithmetics in industry. However, optimizing arithmetic circuits using CSAs is mostly carried out by the designer manually based on his/her design experience, which is a very time-consuming and error-prone task. To overcome this limitation, in this paper we propose an effective synthesis algorithm for solving the problem of finding an allocation of CSAs with a minimal timing for an arithmetic expression. Specifically, we propose a two step approach: (1) allocating a delay-optimal CSA tree for the multi-bit inputs of the arithmetic expression and (2) determining the assignment of the single-bit inputs to carry inputs of the CSAs which leads to a minimal increase of delay of the CSA tree obtained in step (1). For a number of arithmetic expressions, we found that our approach is very effective, reducing the timing of the circuits significantly without increasing the circuit area.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.1
• /
• pp.62-66
• /
• 2009

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the transformation of the sequence of program statements. This transformation does not give any problems in a single-threaded program. However, the transformation gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as Java-Pathfinder do not consider the transformation resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we describe a new technique which is based on SMT solver. The Java Memory Model Simulator based on SMT Solver can compute all possible output of given multi-thread program within one second which, in contrast, Traditional Java Memory Model Simulator takes one minute.

• The KIPS Transactions:PartD
• /
• v.15D no.1
• /
• pp.99-106
• /
• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.

• Journal of radiological science and technology
• /
• v.32 no.2
• /
• pp.195-203
• /
• 2009

Image registration is a fundamental task in image processing used to match two or more images. It gives new information to the radiologists by matching images from different modalities. The objective of this study is to develop 2D image registration algorithm for PET/CT and CT images acquired by different systems at different times. We matched two CT images first (one from standalone CT and the other from PET/CT) that contain affluent anatomical information. Then, we geometrically transformed PET image according to the results of transformation parameters calculated by the previous step. We have used Affine transform to match the target and reference images. For the similarity measure, mutual information was explored. Use of particle swarm algorithm optimized the performance by finding the best matched parameter set within a reasonable amount of time. The results show good agreements of the images between PET/CT and CT. We expect the proposed algorithm can be used not only for PET/CT and CT image registration but also for different multi-modality imaging systems such as SPECT/CT, MRI/PET and so on.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.10
• /
• pp.96-106
• /
• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.