• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.59-69
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• 2007

In this paper, we propose a MIMO-OFDMA (Multi Input Multi Output-Orthogonal Frequency Division Multiple Access) system based on Grassmannian beamforming for performance improvement of downlink real-time traffic transmission in harsh channel conditions with low CIR (Carrier-to-Interference Ratio). In the proposed system to reduce feedback information for the beamforming, we also apply Grassmannian Beamforming. Furthermore, we propose antenna selection scheme which performs the beamforming with more useful transmit antennas. In the proposed system, the optimal combination of transmit antennas with maximum MRT (Maximum Ratio Transmission) beamforming gain, is selected. Simulation results reveal that the proposed MIMO-OFDMA system achieves significant improvement of spectral efficiency in low CIR region as compared to a typical open-loop MIMO-OFDMA system using pseudo-orthogonal space time block code.

• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1584-1602
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• 2024

It is vital to output the required electrical power following various task requirements when the space reactor power supply is operating in orbit. The dynamic performance of the closed Brayton cycle thermoelectric conversion system is initially studied and analyzed. Based on this, a load tracking power regulation method is developed for the liquid metal cooled space reactor power system, which takes into account the inlet temperature of the lithium on the hot side of the intermediate heat exchanger, the filling quantity of helium and xenon, and the input amount of the heat pipe radiator module. After comparing several methods, a power regulation method with fast response speed and strong system stability is obtained. Under various changes in power output, the dynamic response characteristics of the ultra-small liquid metal lithium-cooled space reactor concept scheme are analyzed. The transient operation process of 70 % load power shows that core power variation is within 30 % and core coolant temperature can operate at the set safety temperature. The second loop's helium-xenon working fluid has a 65K temperature change range and a 25 % filling quantity. The lithium at the radiator loop outlet changes by less than ±7 K, and the system's main key parameters change as expected, indicating safety. The core system uses less power during 30 % load power transient operation. According to the response characteristics of various system parameters, under low power operation conditions, the lithium working fluid temperature of the radiator circuit and the high-temperature heat pipe operation temperature are limiting conditions for low-power operation, and multiple system parameters must be coordinated to ensure that the radiator system does not condense the lithium working fluid and the heat pipe.

• Journal of Power Electronics
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• v.13 no.3
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• pp.469-478
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• 2013

This paper proposes a novel scheme for the current controller for the grid-side converter (GSC) of permanent-magnet synchronous generator (PMSG) wind turbines to eliminate the high-order harmonics in the grid currents under grid voltage disturbances. The voltage unbalance and harmonics in three-phase systems cause grid current distortions. In order to mitigate the input current distortions, multi-loop current controllers are applied, where the positive-sequence component is regulated by proportional-integral (PI) controllers, and the negative-sequence and high-order harmonic components are regulated by proportional-resonance (PR) controllers. For extracting the positive/negative-sequence and harmonic components of the grid voltages and currents without a phase delay or magnitude reduction, composite observers are applied, which give faster and more precise estimation results. In addition, an active damping method using PR controllers to damp the grid current component of the resonant frequency is employed to improve the operating stability of VSCs with inductor-capacitor-inductor (LCL) filters. The validity of the proposed method is verified by simulation and experimental results.

• KEPCO Journal on Electric Power and Energy
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• v.8 no.1
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• pp.5-7
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• 2022

KEPCO's plan is undergoing a trial operation to replace the open-loop section with ring main units configuration where underground distribution lines are installed, by linking the multi-way circuit breakers auto (MCA) on the power side of each pad-mounted transformer. However, ring main units application mentioned above may cause the ripple effects, when implementing the configuration without a study of protection coordination. Because ring main units with classical pre-set protection devices contribution in fault condition didn't consider yet. For the reliable ring main units operation, it is necessary to resolve several protection issues such as the protection coordination with substation side, prevention of the transformer inrush current. These issues can radically deteriorate the distribution system reliability Hence, it is essential to design proper protection coordination to reduce these types of problems. This paper presents a scheme of ring main units' configuration and MCA's settings of time-current curves to preserve the performance of protection coordination among the switchgears considering constraints, e.g. prevention of the ripple effects (on the branch section when a transformer failure occurs and the mainline when a branch line failure occurs). It was confirmed that the propagation of the failure for each interrupter segment could be minimized by applying the proposed TCC and the interrupter settings for the MCAs (branch, transformer). Further, it was verified that the undetected area of the distribution automation system (DAS) could be supplemented by having the MCA configurated ring main units operate first, instead of the internal protection equipment in the transformer such as the fuse, STP when a transformer failure occurs.

• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.503-518
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• 2012

In this paper, we propose a complexity-based parallelization method of the sample adaptive offset (SAO) algorithm which is one of HEVC in-loop filters. The SAO algorithm can be regarded as region-based process and the regions are obtained and represented with a quad-tree scheme. A offset to minimize a reconstruction error is sent for each partitioned region. The SAO of the HEVC can be parallelized in data-level. However, because the sizes and complexities of the SAO regions are not regular, workload imbalance occurs with multi-core platform. In this paper, we propose a LCU-based SAO algorithm and a complexity prediction algorithm for each LCU. With the proposed complexity-based LCU processing, we found that the proposed algorithm is faster than the sequential implementation by a factor of 2.38 times. In addition, the proposed algorithm is faster than regular parallel implementation SAO by 21%.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.104-104
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• 2015

Due to the demand of the cold neutron flux in the neutron science and beam utilization technology, the cold neutron source (CNS) has been constructed and operating in the nuclear research reactor all over the world. The majority of the heat load removal scheme in the CNS is two-phase thermosiphon using the liquid hydrogen as a moderator. The CNS moderates thermal neutrons through a cryogenic moderator, liquid hydrogen, into cold neutrons with the generation of the nuclear heat load. The liquid hydrogen in a moderator cell is evaporated for the removal of the generated heat load from the neutron moderation and flows upward into a heat exchanger, where the hydrogen gas is liquefied by the cryogenic helium gas supplied from a helium refrigeration system. The liquefied hydrogen flows down to the moderator cell. To keep the required liquid hydrogen stable in the moderator cell, the CNS consists of an in-pool assembly (IPA) connected with the hydrogen system to handle the required hydrogen gas, the vacuum system to create the thermal insulation, and the helium refrigeration system to provide the cooling capacity. If one of systems is running out of order, the operating research reactor shall be tripped because the integrity of the CNS-IPA is not secured under the full power operation of the reactor. To prevent unscheduled reactor shutdown during a long time because the research reactor has been operating with the multi-purposes, the introduction of the standby cooling system (STS) can be a solution. In this presentation, the design considerations are considered how to design the STS satisfied with the following objectives: (a) to keep the moderator cell less than 350 K during the full power operation of the reactor under loss of the vacuum, loss of the cooling power, loss of common electrical power, or loss of instrument air cases; (b) to circulate smoothly helium gas in the STS circulation loop; (c) to re-start-up the reactor within 1 hour after its trip to avoid the Xenon build-up because more than certain concentration of Xenon makes that the reactor cannot start-up again; (d) to minimize the possibility of the hydrogen-oxygen reaction in the hydrogen boundary.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.8
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• pp.14-25
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• 2002

In this paper, we propose a modified AFC algorithm which is suitable for the implementation of WCDMA reverse link receiver modem. To reduce the complexity, the modified CP-FDD algorithm named 'Normalized CP-FDD' is applied to the AFC loop. The proposed FDD algorithm overcomes the conventional CP-FDD's sensitivity to the variance of input signal amplitude and increases the linear range of S -curve. Therefore, offset frequency estimation using the proposed scheme can be more stable than the conventional method. Unlike IS-95, since pilot symbol in WCDMA is not transmitted continuously, we introduce a moving average filter at the FDD input to increase the number of cross-product. So, tracking speed and stability are improved. For more rapid frequency acquisition and tracking, we adopt a multi-stage tracking mode. Using NCO having ROM table structure, the frequency offset is compensated. We applied the proposed algorithm in the implementation of WCDMA base station modem successfully.

• Journal of Power Electronics
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• v.18 no.2
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• pp.558-572
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• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.