• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.5
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• pp.88-95
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• 2009

This paper is the research on the development of power conversion system for the fuel cell. In composing the DC/DC converters which have high boost voltage ratio, unlike the conventional method a new multi DC/DC converter system is proposed that the diode and the condenser and the reactor can be reduced by connecting the secondary side output of the transformer. In this system the rectifier part and the filter part of the secondary side in the power transformer that is connecting in series are composed into a single module, which is the strong advantage and the number of level can be easily increased. A new variable shift phase switching method is also suggested that it makes possible to reduce the output voltage ripples in the proposed system. All the factors mentioned above have been verified through simulations and experiments, and the proposed converter is considered very useful in the demanded load which requires a wide of the output.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.82-93
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• 2006

In this paper, filters are designed to reduce transients overvoltage in inverter fed high-voltage large-capacity induction motor drive system. Design issues for a LCR filter at the inverter output terminals to reduce the dv/dt of the inverter output pulse and a RC filter at the induction motor input terminals to match the characteristic impedance between cable and induction motor are examined in detail. These filters are modeled to be suitable to high-voltage large-capacity induction motor. The performance of the filter is evaluated through simulation using EMTP(ElectroMagnetic Transients Program). We presented filters that used high voltage large-capacity induction Motor on the basis of this. Effect of the filter is analyzed for variation of the cable length. Characteristics of filters are analyzed to reduce harmonic in voltage waveform of induction motor input terminal. The switching surge voltage became the major cause to occur the insulation failure by serious voltage stress in the stator winding of induction motor. Filter for to mitigate transients overvoltage presents a required component in drive system of high-voltage large-capacity induction motor. Also, proposed filters are proved through simulation using EMTP.

• The KIPS Transactions:PartC
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• v.9C no.6
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• pp.893-902
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• 2002

MPLS enables efficient explicit routing, and thus provides great advantages in supporting traffic engineering. Exploiting this capability, we Propose a load balancing scheme which deploys a multipath routing. It is named LBM (Load Balancing in MPLS networks), and targets at efficient network utilization as well as performance enhancement. LBM establishes multiple LSP (Label Switched Path)s between a pair of ingress-egress routers, and distributes traffic over these LSPs at the new level. Its routing decision is based on both the length and the utilization of the paths. In order to enhance the efficiency of a link usage, a link is limited to be used by shorter paths as its utilization becomes higher Longer paths are considered to be candidate alternative paths as the utilization of shorter paths becomes higher. Simulation experiments are performed in order to compare the performance of LBM to that of static shortest path only scheme as well as the other representative dynamic multipath traffic distribution approaches. The simulation results show that LBM outperforms the compared approaches, and the performance gain is more significant when the traffic distribution among the ingress-egress pairs is non-uniform.

• Journal of Power Electronics
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• v.19 no.4
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• pp.922-933
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• 2019

The arm inductance (AI) of a modular multilevel converter (MMC) affects both the fault and circulating current magnitudes. In addition, it has an impact on the inverter efficiency and harmonic content. In this study, the AI of a three-phase MMC is optimized in a novel way in terms of DC voltage utilization, harmonics and efficiency. This MMC has 10 submodules (SM) per arm and the power circuit topology of the SM is a half-bridge. The optimum AI is adopted and verified in an MMC that has 100 SMs per arm. Then the phase shift (PS) and phase disposition (PD) pulse width modulation (PWM) methods are investigated for better DC voltage utilization, efficiency and harmonics. It is found that similar performances are obtained for both modulation techniques in terms of DC voltage utilization. However, the total harmonic distortion (THD) of the PS-PWM is found to be 0.02%, which is slightly lower than the THD of the PD-PWM at 0.16%. In efficiency calculations, the switching and conduction losses for all of the semiconductor are considered separately and the minimum efficiency of the 100-SM based MMC is found to be 99.62% for the PS-PWM and 99.64% for the PD-PWM with the optimal value of the AI. Simulation results are verified with an experimental prototype of a 6-SM based MMC.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.109-115
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• 2000

In this paper, we propose a new method for power estimation in nodes of multi-level combinational circuits and describe its application to the extraction of common expressions for low power design. Extracting common expressions which is accomplished mostly by the extraction of kernels and common cubes, can be transformed to the problem of rectangle covering. We describe how the newly proposed estimation method can be applied to the rectangle covering problem and show the experimental results with comparisons to the results of SIS-1.2.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.318-323
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• 2004

In this paper, we present a reducing power consumption of a scheduling for reuse module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.12
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• pp.1791-1800
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• 2012

This paper presents effective design schemes for a photovoltaic (PV) and battery hybrid system that includes state-of-the-art technologies such as maximum power point tracking scheme for PV arrays, an effective charging/discharging circuit for batteries, and grid-interfacing power inverters. Compared to commonly-used PV systems, the proposed configuration has more flexibility and autonomy in controlling individual components of the PV-battery hybrid system. This paper also proposes an intelligent coordination scheme for the components of the PV-battery hybrid system to improve the efficiency of renewable energy resources and peak-load management. The proposed algorithm is based on a rule-based expert system that has excellent capability to optimize multi-objective functions. The proposed configuration and algorithms are investigated via switching-level simulation studies of the PV-battery hybrid system.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.161-166
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• 2006

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• ETRI Journal
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• v.45 no.4
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• pp.615-626
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• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.