• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.61-68
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• 2010

In this paper, we investigate the performance of ARQ-aided Time Switched Transmit Diversity (ARQ-TSTD) applying the multi-level control signaling in the WCDMA LCR-TDD system. Proposed ARQ-TSTD system applies the multi-level control signaling scheme in which the receiver sends the response signal (ACK or NACK signal) to the transmitter and defines NACK2 signal for multi-level control. Transmitter utilize the NACK2 control signal to the postponement of transmission and multi-user scheduling scheme proposed by this paper. Simulation results demonstrate that the proposed postponement of transmission and multi-user scheduling scheme yield about 1.3dB, 1.4dB performance gain respectively, compared with the conventional ARQ-TSTD with antenna switching scheme in tenn of the frame error rate (FER) for mobile speed of 3km/h and FER value of 10%. In addition, 14% and 11.5% of throughput gain respectively is shown when Eb/N0=-3dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.4
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• pp.285-301
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• 1988

The symbol error rate equations of multi-level quadrature PRS(QPRS) system have been derived in the individual and composite environment of Gaussian/impulsive noise, cochannel CW interference, carrier offset, phase jitter and fading. And using the derived error rate equations, the probability of error has been evaluated and shown in graphs as functions of carrier to noise power ratio, carrier to interference power ratio, phase error, impulsive index, the ration of Gaussian noise to impulsive noise power component, signal to noise power ration in phase locked loop(PLL), and fading figures. The rseults show that the error rate performances are generally more more degraded by impulsive noise than by Gaussian noise. But on the contrary the erors occurred more frequently by Gaussian noise than impulsive noise in a fading environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Biomolecules & Therapeutics
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• v.29 no.6
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• pp.658-666
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• 2021

Podophyllotoxin (PT), a lignan compound from the roots and rhizomes of Podophyllum peltatum, has diverse pharmacological activities including anticancer effect in several types of cancer. The molecular mechanism of the anticancer effects of PT on colorectal cancer cells has not been reported yet. In this study, we sought to evaluate the anticancer effect of PT on human colorectal cancer HCT116 cells and identify the detailed molecular mechanism. PT inhibited the growth of cells and colony formation in a concentration-dependent manner and induced apoptosis as determined by the annexin V/7-aminoactinomycin D double staining assay. PT-induced apoptosis was accompanied by cell cycle arrest in the G2/M phase and an increase in the generation of reactive oxygen species (ROS). The effects of PT on the induction of ROS and apoptosis were prevented by pretreatment with N-acetyl-L-cysteine (NAC), indicating that an increase in ROS generation mediates the apoptosis of HCT116 cells induced by PT. Furthermore, Western blot analysis showed that PT upregulated the level of phospho (p)-p38 mitogen-activated protein kinase (MAPK). The treatment of SB203580, a p38 inhibitor, strongly prevented the apoptosis induced by PT, suggesting that PT-induced apoptosis involved the p38 MAPK signaling pathway. In addition, PT induced the loss of mitochondrial membrane potential and multi-caspase activation. The results suggested that PT induced cell cycle arrest in the G2/M phase and apoptosis through the p38 MAPK signaling pathway by upregulating ROS in HCT116 cells.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Journal of Broadcast Engineering
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• v.16 no.3
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• pp.520-529
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• 2011

In this paper, we propose the extension of the MPEG-2 Transport Stream (TS) header for efficient adaptation of multi-layer coded video such as scalable video coding (SVC) and multiview video coding (MVC) in the HTTP streaming. First of all, the limit of the existing TS in terms of flexible adaptation of multi-layer video is investigated, and the signaling by extending TS header is proposed to provide efficient adaptation in a TS level. The proposed extension utilizes the private data field in the adaptation field of TS header to signal scalability and/or view information, which enable us to support diverse adaptation that suits underlying constraints of client capabilities, network conditions and user preferences. In short, the extension enables adaptation of scalable video with full scalability as well as view selection of multiview video in a TS level while keeping backward compatibility with the existing TS syntax/semantics. The performance of the proposed extension is compared with the existing adaptation using PID (packet ID) in terms of efficiency and complexity of adaptation. Furthermore, the increase of TS overhead caused by proposed extension is analyzed and an extension scheme to minimized the overhead is proposed.

• Convergence Security Journal
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• v.12 no.1
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• pp.35-42
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• 2012

Increase of data traffic and the advent of new real-time services require to change from the traditional TDM-based (Time Division Multiplexing) networks to the optical networks that soft and dynamic configuration. Voice and lease line services are main service area of the traditional TDM-based networks. This optical network became main infrastructure that offer many channel that can convey data, video, and voice. To provide high resilience against failures, Packet-optical networks must have an ability to maintain an acceptable level of service during network failures. Fast and resource optimized lightpath restoration strategies are urgent requirements for the near future Packet-optical networks with a Generalized Multi-Protocol Label Switching(GMPLS) control plane. The goal of this paper is to provide packet-optical network with a hierarchical multi-layer recovery in order to fast and coordinated restoration in packet-optical network/GMPLS, focusing on new implementation information. The proposed schemes do not need an extension of optical network signaling (routing) protocols for support.