• The Journal of the Korea Contents Association
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• v.11 no.12
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• pp.742-752
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• 2011

Multi-Level Marketing distribution process to reduce occurs in a number of the distribution costs to consumers of reducing its profits outside the area subject to the non-store or stores is the way to a special sale. Japan for the multi-level marketing Article 33 of the Act on Specified Commercial Transactions at or below the regulatory chain is defined as dealers. However, unlike other legislative attention two -dimensional chain for sales transactions are regulated. A chain of Japanese regulations on sales transactions, the definition is very specific and detailed regulations, and the chain is specifically for sales transactions in detail how to take regulatory and regulatory relief of pre- and post- regulatory focus, and the streamlining of regulatory aimed at restrictions on how the implications of such a large country.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.786-799
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• 2021

Road damage detection is important for road maintenance. With the development of deep learning, more and more road damage detection methods have been proposed, such as Fast R-CNN, Faster R-CNN, Mask R-CNN and RetinaNet. However, because shallow and deep layers cannot be extracted at the same time, the existing methods do not perform well in detecting objects with fewer samples. In addition, these methods cannot obtain a highly accurate detecting bounding box. This paper presents a Multi-level Feature Pyramids method based on M2det. Because the feature layer has multi-scale and multi-level architecture, the feature layer containing more information and obvious features can be extracted. Moreover, an attention mechanism is used to improve the accuracy of local boundary boxes in the dataset. Experimental results show that the proposed method is better than the current state-of-the-art methods.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.120-126
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• 2006

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2359-2369
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• 2009

The study on the multi-level inverter has been increasingly progressing to reduce the switching loss and improve the THD of output current in photovoltaic inverter. Recently, the main topics of multi-level inverter are to reduce the number of devices maintaining the power quality. Therefore, the novel topology was proposed for these problem which is composed of the isolated H-bridge multi-level inverter using the three phase low frequency transformer. The proposed multi-level inverter may not be need for a independent DC power, diode and capacitor. Specially, It has a advantage in generating high voltage source. The proposed approach is verified through simulation and experiment.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.7
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• pp.352-360
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• 2003

This paper deals with a simple method in order to analyze and compare the harmonic characteristics in the multi-level inverter. Generally, the magnitude of harmonic components becomes different according to the multi-carrier Pulse Width Modulation(PWM) techniques, the modulation index($M_i$) and the switching frequency The previous papers analyzed the harmonic characteristics from the viewpoint of the space voltage vector. Hence, the calculation of the harmonic vector becomes more difficult and complex in 4-level or over 5-level. However, the proposed method has reduced an amount of calculation and simplified the process of it, using the relationship between the reference voltage and the output phase voltage to the load neutral point. It is applied to the 5-level cascade inverter and the harmonic characteristics for each multi-carrier PWM technique are compared through the simulation.

• Transactions of the Korean Society of Automotive Engineers
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• v.8 no.3
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• pp.151-162
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• 2000

This study is concerned with computerized multi-level substructuring methods and stress analysis of coil springs. The purpose of substructuring methods is to reduce computing time and capacity of computer memory by multiple level reduction of the degrees of freedom in large size problems that are modeled by three dimensional continuum finite elements. In this paper, the spring super element developed is investigated with tension, torsion, and bending of a cylindrical bar in order to verify its accuracy and efficiency for the multi-level substructuring method. And then the algorithm is applied to finite element analysis of coil springs. The result demonstrates the validity of the multi-level substructuring method and the efficiency in computing time and memory by providing good computational results in coil spring analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.337-343
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• 2015

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.17-21
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• 2016

This paper investigates the importance of the computational overhead when machine learning methods, such as SVM, LASSO, AdaBoosting and AdaBagging, are used for automatic security classification.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.291-297
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• 2012

Recently, Switching devices become cheaper, depending on the multi-level inverters are considered as the power-conversion systems for high-power and power-quality demanding applications. The multi-level inverters can reduce the THD(Total Harmonic Distortion) as the output which is similar sinusoidal waveform by synthesizing several capacitor DC voltages. However it has some disadvantages such as increased number of components, complex PWM control method. Therefore, this paper is proposed the new multi-level inverter topology using an new H-bridge output stage with a bidirectional auxiliary switch. The proposed topology is the 4-level 3-phase PWM inverter with less switching part than conventional multi-level inverters and reactive power control possible. In order to understand the new multi-level inverter, topology analysis and switching patterns and modes according to the current loop are described in this paper. The proposed multi-level inverter topology is validated through PSIM simulation and the experimental results are provided from a prototype.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.4
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• pp.195-200
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• 2005

In this paper, we proposed the electric circuit using one common arm of H-Bridge Inverters to reduce the number of switching component in multi-level inverter combined with H-Bridge Inverters and Transformers. and furthermore we suggested the new multi-level PWM inverter using PWM level to reduce THD(Total Harmonic Distortion). and we used the switching method that can be same rate of usage at each transformer. Also, we tested the proposed prototype 9-level inverter to clarify the proposed electric circuit and reasonableness of control signal for the proposed multi-level PWM inverter.