• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.742-745
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• 2005

This paper describes a simple pseudo-random carrier modulation technique for the acoustic noise reduction of the three phase multi-level inverter based motor drives. The proposed method generates a new pseudo-random carrier by randomly synthesizing a carrier with fixed frequency and a carrier with opposition phase. To confirm the validity of the proposed method, a 130v three-phase multi-level inverter was Implemented and tested. The experimental results show that the output line voltage and acoustic noise harmonics spectra of an inverter have broadening effect of harmonics, as only simple synthesis of fixed frequency carries.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.29-32
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• 2001

The application of SRM(Switched Reluctance Motor) is dramatically increasing due to a simple mechanical structure, high efficiency and a good high speed characteristics. To control high conduction ratio in motor operation and regenerative voltage in the generator operation multi-level voltage control is effective. This paper proposes multi-level inverter to have a maximum conduction ratio of SRM. The proposed method is verified by experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.4
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• pp.288-295
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• 2010

Multi-level inverters have drawn much of attention in recent years because it can meet the demand of high power applications and good power quality associated with reduced harmonic distortion. As the number of voltage level increases, field programmable gate arrays (FPGAs) are suitable for the implementation of multi-level modulation algorithm. This paper proposes the implementation method for generating PWM pulses at the three phase diode clamped five-level inverter using FPGA. The strategy for communicating stably the data of three-phase reference voltages between the DSP and FPGA is suggested. The techniques for generating PWM signals based on a multi-carrier modulation method are carried out through the experiments with 32-bit DSP and Cyclone-III FPGA.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.43-51
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• 2010

This paper proposes an analysis of voltage delay and compensation for current control in H-Bridge Multi-Level (HBML) inverters for a medium voltage motor drive with vector control. It is shown that the expansion and modularization capability of the HBML inverter is improved in case of using Phase-Shifted Pulse Width Modulation (PSPWM) since individual inverter modules operate more independently. But, the PSPWM of HBML has a phase difference between reference voltage and real voltage, which can cause instability in the current regulator at high speed where the ratio of the sampling frequency to the output frequency is insufficient. This instability of the current regulator is removed by adding a proposed method which compensate a phase difference between reference voltage and real voltage. The proposed method is suitable for HBML inverter controlled by PSPWM with low switching frequency and high speed motor drive. The validity of the proposed method is verified experimentally on 6,600[V] 1,400[kW] induction motor fed by an 13-level HBML inverter.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.200-201
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• 2005

This paper is analyzed a new modulation method of OSW(Optimized Sine-Wave) modulation strategy for cascaded H-bridge multi-level inverter. The inverter structure was modified with the maximum output voltage level, and the switching angle was calculated easily to adjust the requested Vrms of the output. The suggested modulation method could make output waveform very close to the ideal sine wave, and the THD value was improved also remarkably.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.4
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• pp.161-169
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• 2003

The applications of SRM(Switched Reluctance motor) are dramatically increasing due to a simple mechanical structure, a high efficiency and a high speed drive characteristics. Energy recovery in the regenerative region is very important when SRM is used in traction drive. This is to reduce energy loss during mechanical braking and/or to have a high efficiency drive. To control excitation voltage during motoring and regenerating voltage in the generator operation in the SRM, multi-level voltage control is effective. This paper suggests multi-level inverter which is useful for motoring and regenerative operation. The proposed method is verified through simulations and experiments.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.4
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• pp.161-161
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• 2003

The applications of SRM(Switched Reluctance motor) are dramatically increasing due to a simple mechanical structure, a high efficiency and a high speed drive characteristics. Energy recovery in the regenerative region is very important when SRM is used in traction drive. This is to reduce energy loss during mechanical braking and/or to have a high efficiency drive. To control excitation voltage during motoring and regenerating voltage in the generator operation in the SRM, multi-level voltage control is effective. This paper suggests multi-level inverter which is useful for motoring and regenerative operation. The proposed method is verified through simulations and experiments.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.625-629
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• 2004

This paper presents a systematical approach to study carrier based PWM techniques (CPWM) in diode-clamped and cascade multilevel inverters by using a proposed named multi-modulating pattern method. This method is based on the vector correlation between CPWM and the space vector PWM (SVPWM) and applicable to both multilevel inverter topologies. A CPWM technique can be described in a general mathematical equation, and obtain the same outputs similarly as of the corresponding SVPWM. Control of the fundamental voltage, vector redundancies and phase redundancies in multilevel inverter can be formulated separately in the CPWM equation. The deduced CPWM can obtain the full vector redundancy control, and fully utilize phase redundancy in a cascade inverter In this continued part, it will be deduced correlation between CPWM equations in multi-carrier system and single carrier system, present the mathematical model of voltage source inverter related to the common mode voltage and propose a general algorithm for multi-modulating modulator. The obtained theory will be demonstrated by simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.422-428
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• 2013

Recently, we use a static synchronous compensator(STATCOM) with cascaded H-bride topologies, because it is easy to increase capacity and to reduce total harmonic distortion(THD). When we use equipment for reactive power compensation, dc-link voltage unbalances occur from several reasons although loads are balanced. In the past, switching pattern change of single phase inverter and reference voltage magnitude change of inverter equipped with power sensor have been used for dc-link voltage balance. But previous methods are more complicated and expensive because of additional component costs. Therefore, this paper explains reasons of dc-link voltage unbalance and proposes solution. This solution is complex method that is composed of reference voltage magnitude change of inverter without additional hardware and shifted phase angle of inverter reference voltages change. It proves possibility through 1000[KVA] system simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.99-105
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• 2014

This paper proposes the reliability improvement of H-Bridge Multi-level (HBM) inverter. This reliability can be implemented through modularization of power circuit, distribution of controller, duplication of controller and communication, and continuous operation method in case of power cell failure for driving medium-voltage & high-power induction motor. It is shown that the modularization and expansion characteristics of the HBM inverter are improved since the individual inverter modules operate more independently when using the proposed concept. Also the fault tolerance is increased by using power cell bypass. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.