• 한국진공학회지
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• 제17권2호
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• pp.138-147
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• 2008

RF 스퍼터링 시스템을 이용하여 $SiO_2/TiO_2/ZrO_2$ 광대역 반사방지막을 단계별로 제작하였고, 분광타원계와 $UV-V_{is}$ 분광광도계를 이용하여 박막의 두께, 굴절률 및 투과율 스펙트럼을 300$\sim$900nm의 파장 영역에 걸쳐 측정 및 분석하였다. 측정 및 분석된 박막의 두께, 굴절률 및 투과율 스펙트럼을 설계값과 비교 평가한 결과 각층의 두께, 굴절률의 차이에 따른 투과율의 변화를 분석할 수 있었고, 박막의 두께보다는 굴절률과 굴절률의 분산형태가 투과율의 변화에 더 크게 기여함을 알 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 대한금속재료학회지
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• 제49권5호
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• pp.380-387
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• 2011

Wire brushing, which is a typical surface preparation method for roll bonding, has recently been highlighted as a potentially effective method for surface nanocrystallization. In the present study, the microstructure evolution and hardness of the wire-brushed surface and roll-bonded interface of a 1050 aluminum sheet were investigated. Wire brushing formed protruded layers with a nanocrystalline structure and extremely high surface hardness. After roll bonding, the protruded layers remained as hard layers at the interface. Due to their hardness and brittleness the interface hard layers, can affect the interface bonding properties and also play an important role determining the mechanical properties of multi-layered clad sheets.

• 전자공학회논문지D
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• 제34D권3호
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• pp.17-24
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• 1997

Broad-band RAM's (Radar absorbing materials) are designed by multi-layered lossy dielectrics. The depth, the relative permittivity and the loss tangent of each layer are optimized in order to meet the required reflective power over the specified frequency range using a genetic algorithm. The reflection coefficients are calculated by the continued fraction method. A new population model of the partial initialization method during iterations is applied for the multi-modal functions to enhance the performance of the genetic algorithm. The optimal RAN's are designed by setting the relative permittivity and the loss tangent of the dielectrics as a funtion of the frequency over 5~20GHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.55-56
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• 2006

We investigated the diffraction grating efficiency by the DPSS laser beam wavelength to improve the diffraction efficiency on AsGeSeS & Ag/ AsGeSeS thin film. Diffraction efficiency was obtained from DPSS(532nm)(P:P)polarized laser beam on AsGeSeS, Ag/ AsGeSeS and AsGeSeS/Ag/AsGeSeS thin films. As a result, for the laser beam intensity, 0.24 mW, single AsGeSeS thin film shows the highest value of 0.161% diffraction efficiency at 300 s and for 2.4 mW, it was recorded with the fastest speed of 50 s, which the diffraction grating forming speed is faster than that of 0.24 mW beam. Ag/ AsGeSeS and AsGeSeS/ Ag/ AsGeSeS multi-layered thin film also show the faster grating forming speed at 2.4 mW and higher value of diffraction efficiency at 0.24 mW.

• 한국분말야금학회:학술대회논문집
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• 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part 1
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• pp.254-255
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• 2006

Powder library of pseudo four components Li-Ni-Co-Ti compounds were prepared for exploring the composition region with the single phase of the layer-type structure by using combinatorial high-throuput preparation system "M-ist Combi" based on electrostatic spray deposition method. The new layer-type compounds were found wider composition region than the previous report. This process is promising way to find multi component functional materials.

• 소성∙가공
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• 제19권5호
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• pp.320-324
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• 2010

Multi-Layer Ceramic Circuit(MLCC) in the face of thousands of fine pitch multi hole is processed. However, the fine pitch multi hole has a size of only a few micrometers. Therefore, in order to curtail the measurement time and reduce error, the image processing measurement method is required. So, we proposed an image processing measurement algorithm which is required to accurately measure the fine pitch multi hole. The proposed algorithm gets image of the fine pitch multi hole, extracts object from the image by morphological process, and extracts the parameters of its position and feature by edge detecting process. In addition, we have used the sub-pixel algorithm to improve accuracy. As a result, the proposed algorithm shows 97% test-retest measurement reliability within 2 ${\mu}m$. We found that the algorithm was wellsuited for measuring the fine pitch multi hole.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1537-1540
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• 2003

MEMS technology with micro scale is complete system utilized as the sensor. micro electro device. The metallization of MEMS is very important to transfer the power operating the sensor and signal induced from sensor part. But in the MEMS structures local stress concentration and deformation is often happened by geometrical shape and different constraint on the metallization. Therefore. this paper studies the effect of supporting type and thickness ratio about thin film thickness of the substrate thickness for the residual stress variation caused by thermal load in the multi-layer thin film. Specimens were made from materials such as Al, Au and Cu and uniform thermal load was applied, repeatedly. The residual stress was measured by FEA and nano-indentation using AFM. Generally, the specimen made of Al induced the large residual stress and the 1st layer made of Al reduced the residual stress about half percent than 2nd layer. Specimen made of Cu and Au being the lower thermal expansion coefficient induce the minimum residual stress. Similarly the lowest indentation length was measured in the Au_Cu specimen by nano-indentation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.150.2-150.2
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• 2015

In this study, we analyzed the electric and optical characteristics by using various deposition rate ($0.5{\AA}$, $1.0{\AA}$ and $1.5{\AA}/s$) in order to enhance the performance in organic light-emitting devices (OLED). The organic multi-layer structures were deposited with NPB ($500{\AA}$ as hole transport layer), Alq3 ($600{\AA}$ as electron transport layer and emission layer) and LiF ($8{\AA}$ as electron injection layer) via SUNIC PLUS200 on Glass/ITO substrates. In this experiment, we examined the relationship between porous state of organic deposition and mobility of the organic materials. Among the three deposition rates, $0.5{\AA}/s$ achieved the highest performance of (10,786cd/m2, 4.387cd/A) comparing with that of $1{\AA}/s$ (7,779cd/m2, 3.281cd/A) and $1.5{\AA}/s$ (5,167cd/m2, 2.693cd/A). We confirmed that low deposition rate helps to arrange organic materials densely and to move easily another atomic location using inter-chain transporting by orbital overlap.

• Applied Science and Convergence Technology
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• 제24권2호
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• pp.33-40
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• 2015

$ZrO_2$ and Al-Zr composite oxide film was prepared by vacuum assisted sol-gel dip coating method and anodizing. $ZrO_2$ films annealed above $400^{\circ}C$ have tetragonal structure. $ZrO_2$ layers inside etch pits were successfully coated from the $ZrO_2$ sol. The double layer structures of samples were obtained after being anodized at 100 V to 600 V. From the TEM images, it was found that the outer layer was $Al_2O_3$, the inner layer was multi-layer of $ZrO_2$, Al-Zr composite oxide and Al hydrate. The capacitance of $ZrO_2$ coated foil exhibited about 28.3% higher than that of non-coating foil after being anodized at 100 V. The high capacitance of $ZrO_2$ coated foils anodized at 100 V can be attributed to the relatively high percentage of inner layer in total thickness. The electrical properties, such as withstanding voltage and leakage current of coated and non-coated Al foils showed similar values. From the results, $ZrO_2$ and Al-Zr composite oxide is promising to be used as the partial dielectric of high voltage capacitor to increase the capacitance.