• Korean Journal of Materials Research
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• v.20 no.11
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• pp.606-610
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• 2010

Films consisting of a silicon quantum dot superlattice were fabricated by alternating deposition of silicon rich silicon nitride and $Si_3N_4$ layers using an rf magnetron co-sputtering system. In order to use the silicon quantum dot super lattice structure for third generation multi junction solar cell applications, it is important to control the dot size. Moreover, silicon quantum dots have to be in a regularly spaced array in the dielectric matrix material for in order to allow for effective carrier transport. In this study, therefore, we fabricated silicon quantum dot superlattice films under various conditions and investigated crystallization behavior of the silicon quantum dot super lattice structure. Fourier transform infrared spectroscopy (FTIR) spectra showed an increased intensity of the $840\;cm^{-1}$ peak with increasing annealing temperature due to the increase in the number of Si-N bonds. A more conspicuous characteristic of this process is the increased intensity of the $1100\;cm^{-1}$ peak. This peak was attributed to annealing induced reordering in the films that led to increased Si-$N_4$ bonding. X-ray photoelectron spectroscopy (XPS) analysis showed that peak position was shifted to higher bonding energy as silicon 2p bonding energy changed. This transition is related to the formation of silicon quantum dots. Transmission electron microscopy (TEM) and electron spin resonance (ESR) analysis also confirmed the formation of silicon quantum dots. This study revealed that post annealing at $1100^{\circ}C$ for at least one hour is necessary to precipitate the silicon quantum dots in the $SiN_x$ matrix.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.228-238
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• 1992

An investigation on the step-coverage of PECVD and $O_3$ ThCVD oxides was undertaken to implement into the void-free inter metal dielectric planarization using multi-chamber system for the submicron double level metallization. At various initial aspect ratios the instantaneous aspect ratios were measured through modelling and experiment by depositing the oxides up to $0.9{\mu}m$ in thickness in order to monitor the onset of void formation. The modelling was found to be in a good agreement with the observed instantaneous aspect ratio of TEOS-based PECVD oxide whose re-entrant angle was less than $5^{\circ}$. It is demonstrated that either keeping the instantaneous aspect ratio of PECVD oxide as a first layer less than a factor of 0.8 or employing Ar sputter etch to create sloped oxide edge ensures the void-free planarization after$O_3$ ThCVD oxide deposition whose step-coverage is superior to PECVD oxide. It has been observed that $O_3$ ThCVD oxide etchback scheme has shown higher yield of via contact chain than non etchback process, with resistance per via contact of $0.1~0.3{\Omega}/{\mu}m^2$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.23 no.1
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• pp.14-19
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• 2013

We have successfully synthesized $Bi_{4-x}La_xTi_3O_{12}$ (x~2) having Aurivillius-type layered perovskite structure from exfoliated layered perovskite oxide of $K_2La_2Ti_3O_{10}$ with Ruddlesden-Popper structure. The reaction between the exfoliated lanthanum titanate nanosheets and BiOCl nanocrystal resulted in the formation of polycrystalline $Bi_{4-x}La_xTi_3O_{12}$ (x~2) after heating above $700^{\circ}C$. Colloidal suspension of the nanosheets could be obtained by intercalating ethylamine (EA) into the protonated lanthanum titanate, $H_2La_2Ti_3O_{10}$, derived from $K_2La_2Ti_3O_{10}$. Transmission electron microscopic (TEM) analysis show that the exfoliated lanthanium titanate nanosheets have a thickness of a few nano meters. According to X-ray diffraction (XRD) analysis, the exfoliated lanthanium titanate was found to be transformed into $Bi_{4-x}La_xTi_3O_{12}$ (x~2) after restacking with BiOCl and subsequent thermal treatment at > $700^{\circ}C$.

• Applied Chemistry for Engineering
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• v.24 no.3
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• pp.219-226
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• 2013

Organic semiconductor-based soft electronics has potential advantages for next-generation electronics and displays, which request mobile convenience, flexibility, light-weight, large area, etc. Organic field-effect transistors (OFET) are core elements for soft electronic applications, such as e-paper, e-book, smart card, RFID tag, photovoltaics, portable computer, sensor, memory, etc. An optimal multi-layered structure of organic semiconductor, insulator, and electrodes is required to achieve high-performance OFET. Since most organic semiconductors are self-assembled structures with weak van der Waals forces during film formation, their crystalline structures and orientation are significantly affected by environmental conditions, specifically, substrate properties of surface energy and roughness, changing the corresponding OFET. Organo-compatible insulators and surface treatments can induce the crystal structure and orientation of solution- or vacuum-processable organic semiconductors preferential to the charge-carrier transport in OFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.5
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• pp.944-949
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• 2015

This study proposed a patch antenna with a MIMO structure which is applicable for wireless communication equipment by combining a single patch antenna with a multi port. The proposed MIMO patch antenna was designed through the TRF-45 substrate with a relative permittivity of 4.5, loss tangent equal to 0.0035 and dielectric high of 1.6 mm, and the center frequency of the antenna was 2.45 GHz in the ISM (Industrial Scientific and Medical) band. The proposed MIMO patch antenna had a 500 MHz bandwidth from 2.16 ~ 2.66 GHz and 24.1% fractional bandwidth. The return loss and VSWR were -62.05 dB, 1.01 at the ISM bandwidth of 2.45 GHz. The Wibro band of 2.3 GHz was -17.43 dB, 1.33, the WiFi band of 2.4 GHz was -31.89 dB, 1.05, and the WiMax band of 2.5 GHz was -36.47 dB, 1.03. The radiation patterns included in the bandwidth were directional, and the WiBro band of 2.3 GHzhad a gain of 4.22 dBi, the WiFi band of 2.4 GHz had a gain of 4.12 dBi, the ISM band of 2.45 GHz had a gain of 4.06dBi, and the WiMax band of 2.5 GHz had a gain of 3.9 6dBi.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.97-105
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• 2020

Recently, as the data speed and operating frequencies of Ethernet keeps increasing, electro magnetic interference (EMI) also becomes increasing. The generation of such EMI will cause malfunction of near electronic devices. In this study, EMI filters were applied to reduce the EMI generated by DC-DC SMPS (switching mode power supply), which is the main cause of EMI generation of Ethernet switch. As the EMI filter, MLCCs with excellent withstanding voltage characteristics were used, which had advantages in miniaturization and mass production. Two types of EMI MLCC filters were used, which are X-capacitor and X, Y-capacitor. X-capacitor was composed of 2 MLCCs with 10 nF and 100 nF capacity and 1 Mylar capacitor. Y-capacitor was consisted of 6 MLCCs with a capacity of 27 nF. When only X-capacitor was applied as EMI filter, the conductive EMI field strength exceeded the allowable limit in frequency range of 150 kHz ~ 30 MHz. The radiative EMI also showed high EMI strength and very small allowable margin at the specific frequencies. When the X and Y-capacitors were applied, the conductive EMI was greatly reduced, and the radiation EMI was also found to have sufficient margin. In addition, X, Y-capacitors showed very high insulation resistance and withstanding resistance performances. In conclusion, EMI X, Y-capacitors using MLCCs reduced the EMI noise effectively and showed excellent electrical reliability.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.78-83
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• 2005

Nanometric crystalline silicon (no-Si) embedded in dielectric medium has been paid attention as an efficient light emitting center for more than a decade. In nc-Si, excitonic electron-hole pairs are considered to attribute to radiative recombination. However the surface defects surrounding no-Si is one of non-radiative decay paths competing with the radiative band edge transition, ultimately which makes the emission efficiency of no-Si very poor. In order to passivate those defects - dangling bonds in the $Si:SiO_2$ interface, hydrogen is usually utilized. The luminescence yield from no-Si is dramatically enhanced by defect termination. However due to relatively high mobility of hydrogen in a matrix, hydrogen-terminated no-Si may no longer sustain the enhancement effect on subsequent thermal processes. Therefore instead of easily reversible hydrogen, phosphorus was introduced by ion implantation, expecting to have the same enhancement effect and to be more resistive against succeeding thermal treatments. Samples were Prepared by 400 keV Si implantation with doses of $1\times10^{17}\;Si/cm^2$ and by multi-energy Phosphorus implantation to make relatively uniform phosphorus concentration in the region where implanted Si ions are distributed. Crystalline silicon was precipitated by annealing at $1,100^{\circ}C$ for 2 hours in Ar environment and subsequent annealing were performed for an hour in Ar at a few temperature stages up to $1,000^{\circ}C$ to show improved thermal resistance. Experimental data such as enhancement effect of PL yield, decay time, peak shift for the phosphorus implanted nc-Si are shown, and the possible mechanisms are discussed as well.