• Title/Summary/Keyword: Multi-decoder

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A study on Korean multi-turn response generation using generative and retrieval model (생성 모델과 검색 모델을 이용한 한국어 멀티턴 응답 생성 연구)

  • Lee, Hodong;Lee, Jongmin;Seo, Jaehyung;Jang, Yoonna;Lim, Heuiseok
    • Journal of the Korea Convergence Society
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    • v.13 no.1
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    • pp.13-21
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    • 2022
  • Recent deep learning-based research shows excellent performance in most natural language processing (NLP) fields with pre-trained language models. In particular, the auto-encoder-based language model proves its excellent performance and usefulness in various fields of Korean language understanding. However, the decoder-based Korean generative model even suffers from generating simple sentences. Also, there is few detailed research and data for the field of conversation where generative models are most commonly utilized. Therefore, this paper constructs multi-turn dialogue data for a Korean generative model. In addition, we compare and analyze the performance by improving the dialogue ability of the generative model through transfer learning. In addition, we propose a method of supplementing the insufficient dialogue generation ability of the model by extracting recommended response candidates from external knowledge information through a retrival model.

Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic (중복 다치논리를 이용한 20 Gb/s CMOS 디멀티플렉서 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.3
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    • pp.135-140
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    • 2008
  • This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

Multi-dimensional DC-free trellis codes based on tow-dimensional constellation (2차원 성상도를 이용한 다차원 무직류 격자형부호)

  • 정창기;황성준;주언경
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.3
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    • pp.47-53
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    • 1998
  • Multi-dimensional DC-free trellis codes based on two-dimensional constellation which can be omplemented more easily than conventional codes are proposed and their performances are analyzed in this paper. 2N-dimensional constellation of the proposed codes is constructed by concatenating N 2-dimensional constellation. Thus, for the proposed codes, information bits can be assigned easily to each signal point of the 2-dimensional consteellation and DC-free characteristic can be simply obtained by the symmetric structure of the constellation. In addition, since Viterbi decoder can calculate multi-dimensional Euchlidean distance between signals by simple sum of each 2-dimensional Euclidean distanc, decoding complexity can be reduced. The performance analysis shows that the proposed codes have almost same spectral characteristic and error performance as compared with conventional codes. However, the complexity is shown to be reduced further due to the construction method of contellation and the simple decoding algorithm of the proposed codes.

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Multi-focus Image Fusion using Fully Convolutional Two-stream Network for Visual Sensors

  • Xu, Kaiping;Qin, Zheng;Wang, Guolong;Zhang, Huidi;Huang, Kai;Ye, Shuxiong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.5
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    • pp.2253-2272
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    • 2018
  • We propose a deep learning method for multi-focus image fusion. Unlike most existing pixel-level fusion methods, either in spatial domain or in transform domain, our method directly learns an end-to-end fully convolutional two-stream network. The framework maps a pair of different focus images to a clean version, with a chain of convolutional layers, fusion layer and deconvolutional layers. Our deep fusion model has advantages of efficiency and robustness, yet demonstrates state-of-art fusion quality. We explore different parameter settings to achieve trade-offs between performance and speed. Moreover, the experiment results on our training dataset show that our network can achieve good performance with subjective visual perception and objective assessment metrics.

Multi-stage Transformer for Video Anomaly Detection

  • Viet-Tuan Le;Khuong G. T. Diep;Tae-Seok Kim;Yong-Guk Kim
    • Proceedings of the Korea Information Processing Society Conference
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    • 2023.11a
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    • pp.648-651
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    • 2023
  • Video anomaly detection aims to detect abnormal events. Motivated by the power of transformers recently shown in vision tasks, we propose a novel transformer-based network for video anomaly detection. To capture long-range information in video, we employ a multi-scale transformer as an encoder. A convolutional decoder is utilized to predict the future frame from the extracted multi-scale feature maps. The proposed method is evaluated on three benchmark datasets: USCD Ped2, CUHK Avenue, and ShanghaiTech. The results show that the proposed method achieves better performance compared to recent methods.

A Parallelization Technique with Integrated Multi-Threading for Video Decoding on Multi-core Systems

  • Hong, Jung-Hyun;Kim, Won-Jin;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.10
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    • pp.2479-2496
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    • 2013
  • Increasing demand for Full High-Definition (FHD) video and Ultra High-Definition (UHD) video services has led to active research on high speed video processing. Widespread deployment of multi-core systems has accelerated studies on high resolution video processing based on parallelization of multimedia software. Even if parallelization of a specific decoding step may improve decoding performance partially, such partial parallelization may not result in sufficient performance improvement. Particularly, entropy decoding has often been considered separately from other decoding steps since the entropy decoding step could not be parallelized easily. In this paper, we propose a parallelization technique called Integrated Multi-Threaded Parallelization (IMTP) which takes parallelization of the entropy decoding step, with other decoding steps, into consideration in an integrated fashion. We used the Simultaneous Multi-Threading (SMT) technique with appropriate thread scheduling techniques to achieve the best performance for the entire decoding step. The speedup of the proposed IMTP method is up to 3.35 times faster with respect to the entire decoding time over a conventional decoding technique for H.264/AVC videos.

Distributed Multi-view Video Coding Based on Illumination Compensation (조명보상 기반 분산 다시점 비디오 코딩)

  • Park, Sea-Nae;Sim, Dong-Gyu;Jeon, Byeung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.6
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    • pp.17-26
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    • 2008
  • In this paper, we propose a distributed multi-view video coding method employing illumination compensation for multi-view video coding. Distributed multi-view video coding (DMVC) methods can be classified either into a temporal or an inter-view interpolation-based ones according to ways to generate side information. DMVC with inter-view interpolation utilizes characteristics of multi-view videos to improve coding efficiency of the DMVC by using side information based on the inter-view interpolation. However, mismatch of camera parameters and illumination change between two views could bring about inaccurate side information generation. In this paper, a modified distributed multi-view coding method is presented by applying illumination compensation in generating the side information. In the proposed encoder system, in addition to parity bits for AC coefficients, DC coefficients are transmitted as well to the decoder side. By doing so, the decoder can generate more accurate side information by compensating illumination changes with the transmitted DC coefficients. We found that the proposed algorithm is $0.1{\sim}0.2\;dB$ better than the conventional algorithm that does not make use of illumination compensation.

A 500MHz 1.1㎱ 32kb SRAM Macro with Selective Bit-line Precharge Scheme (선택적 프리차지 방법을 갖는 500MHz 1.1㎱ 32kb SRAM 마크로 설계)

  • 김세준;장일권곽계달
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.699-702
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    • 1998
  • This paper presents a 500MHz 1.1㎱ 32kb synchronous CMOS SRAM macro using $0.35\mu\textrm{m}$ CMOS technology. In order to operate at high frequency and reduce power dissipation, the designed SRAM macro is realized with optimized decoder, multi-point sense amplifier(MPSA), selective precharge scheme and etc. Optimized decorder and MPSA respectively reduce 50% and 40% of delay time. Also, a selective precharge scheme reduces 80% of power dissipation in that part.

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Adaptive PRML Core Development for Optical Disk Playback (광 디스크 재생을 위한 적응형 PRML 코어 개발에 관한 연구)

  • 박현수;김민철;김기현;심재성;서중언;이정현
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.39-42
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    • 2002
  • A new adaptive PRML architecture, considered not only DVD-ROM but also DVD-Multi including DVD-RAM as well, is presented to demonstrate its superiority over the conventional analog channel in a DVD system. For this new architecture, channel adaptation algorithm using gain controlled type of FIR filter, and asymmetry compensation algorithm using expected level adaptation of viterbi decoder are presented. In addition, a method of modelling the disk tilt and asymmetrical read-back signal are discussed.

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The viterbi decoder implementation with efficient structure for real-time Coded Orthogonal Frequency Division Multiplexing (실시간 COFDM시스템을 위한 효율적인 구조를 갖는 비터비 디코더 설계)

  • Hwang Jong-Hee;Lee Seung-Yerl;Kim Dong-Sun;Chung Duck-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.2 s.332
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    • pp.61-74
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    • 2005
  • Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.