• ETRI Journal
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• v.36 no.4
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• pp.682-685
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• 2014

In this letter, we propose an efficient near-optimal detection scheme (that makes use of a generalized sphere decoder (GSD)) for blind multi-user multiple-input multiple-output (MU-MIMO) systems. In practical MU-MIMO systems, a receiver suffers from interference because the precoding matrix, the result of the precoding technique used, is quantized with limited feedback and is thus imperfect. The proposed scheme can achieve near-optimal performance with low complexity by using a GSD to detect several additional interference signals. In addition, the proposed scheme is suitable for use in blind systems.

• Journal of Broadcast Engineering
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• v.11 no.1 s.30
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• pp.116-129
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• 2006

The progress of data transmission technology through the Internet has spread a variety of realistic contents. One of such contents is multi-view video that is acquired from multiple camera sensors. In general, the multi-view video processing requires encoders and decoders as many as the number of cameras, and thus the processing complexity results in difficulties of practical implementation. To solve for this problem, this paper considers a simple multi-view system utilizing a single encoder and a single decoder. In the encoder side, input multi-view YUV sequences are combined on GOP units by a video mixer. Then, the mixed sequence is compressed by a single H.264/AVC encoder. The decoding is composed of a single decoder and a scheduler controling the decoding process. The goal of the scheduler is to assign approximately identical number of decoded frames to each view sequence by estimating the decoder utilization of a Gap and subsequently applying frame skip algorithms. Furthermore, in the frame skip, efficient frame selection algorithms are studied for H.264/AVC baseline and main profiles based upon a cost function that is related to perceived video quality. Our proposed method has been performed on various multi-view test sequences adopted by MPEG 3DAV. Experimental results show that approximately identical decoder utilization is achieved for each view sequence so that each view sequence is fairly displayed. As well, the performance of the proposed method is examined in terms of bit-rate and PSNR using a rate-distortion curve.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1C
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• pp.34-42
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• 2007

The sphere decoder (SD) has recently been proposed to perform maximum likelihood (ML) decoding for multi-input multi-output systems. Employing a 'breadth-first' searching algorithm for closet points in a lattice, we propose a novel ML decoding scheme for multi-input multi-output systems. Simulation results show that the proposed scheme has the same bit error rate performance as the conventional ML decoders while allowing significantly lower computational burden than the SD.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.74-83
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• 2023

In this paper, we propose an image compression scheme which uses a demosaicking network and a channel-wise decoder in the decoding network. For the demosaicing network, we use as the input a colored mosaiced pattern rather than the well-known Bayer pattern. The use of a colored mosaiced pattern results in the mosaiced image containing a greater amount of information pertaining to the original image. Therefore, it contributes to result in a better color reconstruction. The channel-wise decoder is composed of multiple decoders where each decoder is responsible for each channel in the color image, i.e., the R, G, and B channels. The encoder and decoder are both implemented by wavelet based auto-encoders for better performance. Experimental results verify that the separated channel-wise decoders and the colored mosaic pattern produce a better reconstructed color image than a single decoder. When combining the colored CFA with the multi-decoder, the PSNR metric exhibits an increase of over 2dB for three-times compression and approximately 0.6dB for twelve-times compression compared to the Bayer CFA with a single decoder. Therefore, the compression rate is also increased with the proposed method than with the method using a single decoder on the Bayer patterned mosaic image.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.132-140
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• 1994

In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.4
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• pp.477-482
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• 2007

This paper presents an audio decoder architecture which can decode AC-3 and MPEG-2 audio bit-streams efficiently. MPEG-2 synthesis filtering is modified by the 32-point FFT to share the common data path with the AC-3's. A programmable Audio DSP core and a hardwired common synthesis tilter are incorporated for effective decoding of two different formats.