• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of The Korea Institute of Healthcare Architecture
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• v.18 no.3
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• pp.41-49
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• 2012

Most large-sized and tall-risen general hospitals of today fairly depend on in-patient wards in designing hospital styles. The core planning for the efficient movements of various people in the words should take into account the sustainable connections between/among the floors, as well as hospital structures and mechanical functions. This study sampled for the study 19 hospital in-patient wards and investigated their flat-core styles. It was found out that hospital structures are changing from symmetrical styles of triangles, quadrangles and rectangles through bending, configuring, transforming to efficient new styles. Symmetrically quadrangled flat-styles are made of multi-cores spread with main an sub-cores. In contrast, symmetrically triangled flat-styles place the open place in the middle in order to prevent from its deepening, and widened the depth line through changing the outdoor top point. Non-symmetrical rectangles minimized the depth value to maintain the recent styles used in the wards, and tended to prefer the transformed styles of quadrangles. The double-corridors easily transshaped from mono corridors reveals the triangled, W-shaped, or Y-shaped figures. The site area ratio of the cores is 11.95% in average. The number of beds which one elevator covers is 66.51 beds in average, and the size of site area which one elevator covers 216.68m. Most cores on the base floor clustered around the average value, with more than 1000 beds shoes 12.83%, does 12.93%, does 14.64%, does 14.58%, which says that the core ratio increases according to hospital beds.

• The Bulletin of The Korean Astronomical Society
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• v.41 no.2
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• pp.38.2-38.2
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• 2016

How dense cores and filaments in molecular clouds form is one of key questions in star formation. To challenge this issue we started to make a systematic mapping survey of nearby molecular clouds in various environments with TRAO 14m telescope equipped with 16 beam array, in high ($N_2H^+$, $HCO^+$ 1-0) and low ($C^{18}O$, $^{13}CO$ 1-0) density tracers (TRAO Multi-beam Legacy Survey of Nearby Filamentary Molecular Clouds, PI: C. W. Lee). We pursue to dynamically and chemically understand how filaments, dense cores, and stars form under different environments. We have performed On-The-Fly (OTF) mapping observations toward L1251, southern part of Perseus molecular cloud, and Serpens main molecular cloud from January to May, 2016. In total, ~3.5 square degree area map of $^{13}CO$ and $C^{18}O$ was simultaneously obtained with S/N of >10 in a velocity resolution of ~0.2 km/s. Dense core regions of ~1.7 square degree area where $C^{18}O$ 1-0 line is strongly detected were also mapped in $N_2H^+$ 1-0 and $HCO^+$ 1-0. The L1251 and Perseus MC are known to be low- to intermediate-mass star-forming clouds, while the Serpens MC is an active low-mass star-forming cloud. The observed molecular filaments will help to understand how the filaments, cores and eventually stars form in a low- and/or intermediate-mass star-forming environment. In this talk, I'll give a brief report on the observation and show preliminary results of Perseus MC.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.11
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• pp.1541-1543
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• 2013

This paper presents a spherical motor which can control in multi-degree of freedom operation. The spherical motor has been researched by many types of structure. Thhis paper shows a spherical shaped airgap and surfaced permanent magnets. Especially, The motor consists of dual rotor cores. Unlike a cylindrical motor, the spherical motor design can be considered with azimuth direction on spherical coordinates. Therefore the permanent magnet surfaced on the rotor need to be designed optimally in order to generate a sinusoidal magnetic flux density in the airgap. This paper presents results of optimal design for reducing torque ripple of the multi-degree of freedom spherical motor.

• International Journal of High-Rise Buildings
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• v.6 no.3
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• pp.271-277
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• 2017

Safety, livability, and efficiency are the three prominent problems of tall buildings, which are also the severe challenges to designers. We proposed the idea of building the sky town to solve these problems, which can be summarized in two sentences, one is tall building multi-storised, and another one is vertical facilities municipal-infrastructurised. The tall building can be horizontally cut into several multi-storey buildings by some large platforms. The platform extends a certain width to block the fire from spreading. Tall buildings are connected together as a group. One of them is a traffic core, which is used for vertical transportation and MEP. It connects to traffic center such as metro, while most of the other tall buildings' cores can be very much released, so as to achieve maximum efficiency of floor usable area and to give good traffic organization. By combining traffic core, platforms, and multi-storey buildings' inner traffic, a transportation network is formed. Finally, we refer to the design of Raffles City Chongqing to make a sketch of sky town.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.10-16
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• 2018

The task of consolidating server workloads is critical for the efficiency of a datacenter in terms of reducing costs. However, as a greater number of workloads are consolidated in a single server, the performance of workloads might be degraded due to their contention to the limited shared resources. To reduce the performance degradation, scheduling for mitigating the contention of shared resources is necessary. In this paper, we present the Dynamic Voltage Frequency Scaling (DVFS) based memory-contention aware scheduling method for multi-threaded workloads. The proposed method uses two approaches: running memory-intensive threads on the limited cores to avoid concurrent memory accesses, and reducing the frequencies of the cores that run memory-intensive threads. With the proposed algorithm, we increased performance by 43% and reduced power consumption by 38% compared to the Completely Fair Scheduler(CFS), the default scheduler of Linux.

• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.1-11
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• 2018

Discrete event system specification (DEVS) has been used in many simulations including hybrid systems featuring both discrete and continuous behavior that require a lot of time to get results. Therefore, in this study, we proposed the acceleration of a DEVS-based hybrid system simulation using multi-cores and GPUs tightly coupled computing. We analyzed the proposed heterogeneous computing of the simulation in terms of the configuration of the target device, changing simulation parameters, and power consumption for efficient simulation. The result revealed that the proposed architecture offers an advantage for high-performance simulation in terms of execution time, although more power consumption is required. With these results, we discovered that our approach is applicable in hybrid system simulation, and we demonstrated the possibility of optimized hardware distribution in terms of power consumption versus execution time via experiments in the proposed architecture.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.1-10
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• 2011

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.289-293
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• 2016

As more mobile devices are equipped with multi-core CPUs and are required to execute many compute-intensive multimedia applications, it is important to optimize the systems, considering the underlying parallel hardware architecture. In this paper, we implement and optimize ray-tracing application tailored to a given mobile computing platform with multiple heterogeneous processing elements. In this paper, a lightweight ray-tracing application is specified and implemented in Kahn process network (KPN) model-of-computation, which is known to be suitable for the description of real-time applications. We take an open-source C/C++ implementation of ray-tracing and adapt it to KPN description in the Distributed Application Layer framework. Then, several possible configurations are evaluated in the target mobile computing platform (Exynos 5422), where eight heterogeneous ARM cores are integrated. We derive the optimal degree of parallelism and a suitable distribution of the replicated tasks tailored to the target architecture.