• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1478-1490
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• 2011

Recently, multi-core processors have been drawing significant interest from the embedded systems research and industry communities due mainly to their potential for achieving high performance and fault-tolerance at low cost in such products as automobiles and cell phones. To process multimedia data, a scheduling algorithm is required to meet timing constraints of periodic tasks in the system. Though Pfair scheduling algorithm can meet all the timing constraints while achieving 100% utilization on multi-core based system theoretically, however, the algorithm incurs high scheduling overheads including frequent core migrations and system-wide synchronizations. To mitigate the problems, we propose a real-time scheduling algorithm for multi-core based system so that system-wide scheduling is performed only when it is absolutely necessary. Otherwise the proposed algorithm performs scheduling within each core independently. The experimental results by extensive simulations show that the proposed algorithm dramatically reduces the scheduling overheads up to as negligible one when the utilization is under 80%.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5465-5480
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• 2018

Energy-efficient task scheduling on multi-core server is a fundamental issue in green cloud computing. Multi-core processors are widely used in mobile devices, personal computers, and servers. Existing energy efficient task scheduling methods chiefly focus on reducing the energy consumption of the processor itself, and assume that the cores of the processor are controlled independently. However, the cores of some processors in the market are divided into several voltage islands, in each of which the cores must operate on the same status, and the cost of the server includes not only energy cost of the processor but also the energy of other components of the server and the cost of user waiting time. In this paper, we propose a cost-aware scheduling algorithm ICAS for computation intensive tasks on multi-core server. Tasks are first allocated to cores, and optimal frequency of each core is computed, and the frequency of each voltage island is finally determined. The experiments' results show the cost of ICAS is much lower than the existing method.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Transactions of the Korean Society of Automotive Engineers
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• v.24 no.2
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• pp.127-136
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• 2016

The camera based object detection systems should satisfy the recognition performance as well as real-time constraints. Particularly, in safety-critical systems such as Autonomous Emergency Braking (AEB), the real-time constraints significantly affects the system performance. Recently, multi-core processors and system-on-chip technologies are widely used to accelerate the object detection algorithm by distributing computational loads. However, due to the advanced hardware, the complexity of system architecture is increased even though additional hardwares improve the real-time performance. The increased complexity also cause difficulty in migration of existing algorithms and development of new algorithms. In this paper, to improve real-time performance and design complexity, a task scheduling strategy is proposed for visual object tracking systems. The real-time performance of the vision algorithm is increased by applying pipelining to task scheduling in a multi-core processor. Finally, the proposed task scheduling algorithm is applied to crosswalk detection and tracking system to prove the effectiveness of the proposed strategy.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.7
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• pp.4545-4553
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• 2014

Mobile GPU has led to the rapid development of smart phone graphic technology. Most recent smart phones are equipped with high-performance multi-core GPU. How a multi-core mobile GPU can be utilized efficiently will be a critical issue for improving the smart phone performance. On the other hand, most current research has focused on a single-core mobile GPU; studies of multi-core mobile GPU are rare. In this paper, the job scheduling patterns and the efficiency of multi-core mobile GPU are analyzed. In the profiling result, despite the higher number of GPU cores, the total processing time required for certain graphics applications were increased. In addition, when GPU is processing for 3D games, a substantial amount of overhead is caused by communication between not only the CPU and GPU, but also within the GPUs. These results confirmed that more active research for multi-core mobile GPU should be performed to optimize the present mobile GPUs.

• Journal of KIISE
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• v.44 no.3
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• pp.223-231
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• 2017

In this paper, we study the performance of recently popular multi-core systems in mobiles. Previous research on the multi-core performance usually focused on the desktop PC. However, there is enough scope to further analyze heterogeneous multi-core systems. Therefore, by extending homogeneous multi-core systems, we analyze the heterogeneous multi-core systems using Size Interval Task Allocation (SITA) for job allocation, and Shortest Remaining Processing Time (SRPT) scheduling, for each individual core. We propose a new computational method regarding the cutoff point, which is crucial in analyzing SITA, by calculating the sojourn time. This facilitate easy and accurate calculation of the sojourn time. We further confirm our analysis through the ESESC simulator that provides actual measurements.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.1
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• pp.1-8
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• 2016

We proposed a load unbalancing scheduling method for energy-efficient multi-core embedded systems considering DVFS (Dynamic Voltage/Frequency Scaling) power consumption and task characteristics. It is a new kind of scheduler which combines load balancing and load unbalancing technique. The purpose of the method is to effectively utilize energy without much effect in performance. In this paper, we conduct experiments on energy consumption and performance using the previous load balancing and unbalancing techniques and our proposed technique. The proposed technique reduced energy consumption more than 13.7% when compared to other algorithms. As a result, the proposed technique shows low energy consumption without much decline in the performance and is adequate for energy-efficient multi-core embedded systems.

• Journal of Electrical Engineering and Technology
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• v.10 no.6
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• pp.2406-2412
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• 2015

Multi-user multi-input multi-output (MU-MIMO) system has attracted the 4^th generation wireless network as one of core technique for performance enrichment. In this system rate control is a challenging problem and another problem is optimization. Proper scheduling can resolve these problems by deciding which set of user and at which rate the users send their data. This paper proposes a new multi-parameter based scheduling (MPS) for downlink multi-user multiple-input multiple-output (MU-MIMO) system under space-time block coding (STBC) transmissions. Goal of this MPS scheme is to offer improved link level performance in terms of a low average bit error rate (BER), high packet delivery ratio (PDR) with improved resource utilization and service fairness among the user. This scheme allows the set of users to send data based on their channel quality and their demand rates. Simulation compares the MPS performance with other scheduling scheme such as fair scheduling (FS), normalized priority scheduling (NPS) and threshold based fair scheduling (TFS). The results obtained prove that MPS has significant improvement in average BER performance with improved resource utilization and fairness as compared to the other scheduling scheme.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.487-501
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• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.11-20
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• 2011

In this paper, we propose an optimal scheduling scheme that minimizes the energy consumption of a real-time video task on the multi-core platform supporting dynamic voltage and frequency scaling. Exploiting parallel execution on multiple cores for less energy consumption, the propose scheme allocates an appropriate number of cores to the task execution, turns off the power of unused cores, and assigns the lowest clock frequency meeting the deadline. Our experiments show that the proposed scheme saves a significant amount of energy, up to 67% and 89% of energy consumed by two previous methods that execute the task on a single core and on all cores respectively.