• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.338-343
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• 2006

This paper describes about the design concept and the architecture of an economic VPN system which can perform fast crypto operations with cheap cost. The essence of the proposed system architecture is consisting of the system with two companion chips dedicated to VPN: one chip is a multi-purpose network processor for security machine and the other is a crypto acceleration chip which encrypt and decrypt network packets in a high speed. This study also addresses about some realizations that is required for fast prototyping such as the porting of an operating system, the establishment of compiler tool chain, the implementation of device drivers and the design of IPSec security engine. Especially, the second chip supports the most time consuming block cipher algorithms including 3DES, AES, and SEED and its performance was evaluated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.57-62
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• 2011

In this paper, an efficient architecture for MFVLD(Multi-Format Variable Length Decoder) which can process H.264, MPEG-2, MPEG-4, AVS, VC-1 bitstream is proposed. The proposed MF-VLD is designed to be adapted to the MPSOC (Multi-processor System on Chip) architecture, uses bit-plane algorithm for the processing of inverse quantized data to reduce the width of AHB bus. External SDRAM is used to minimize the internal memory size. In this architecture, the adding or removing each variable length decoder can be easily done by using multiplexor. The designed MF-VLD can be operated in 200MHz at 0.18um process. The gate size is 657K gate and internal memory size is 27Kbyte.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.6
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• pp.375-382
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• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.873-877
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• 1997

This paper presents experimental results to know the charcteristics of machined surface due to cutter runout. Cutter runout is a common but undesirable phenomenon in multi-tooth machining such as end-milling process because it introduces variable chip loading to insert which results in a accelerated tool wear, amplification of force variation and hence enargement vibration amplitude. To develop in-proess cutter runout compensation system, set-up the micro-positoning mechanism which is based on piezoelectric translator embeded in the work holder to manipulate the depth of cut in real-time. And feasibility test of system was done under the various experimental cutting conditions. This results provide lots of information to build-up the precision machining technology.

• Mass Spectrometry Letters
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• v.1 no.1
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• pp.21-24
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• 2010

The development of clinical biomarkers involves discovery, verification, and validation. Recently, multiple reaction monitoring (MRM) coupled with stable isotope dilution mass spectrometry (IDMS) has shown considerable promise for the direct quantification of proteins in clinical samples. In particular, multiple biomarkers have been tracked in a single experiment using MRM-based MS approaches combined with liquid chromatography. We report here a highly reproducible, quantitative, and dynamic MRM system for validating multi-biomarker proteins using Nanoflow HPLC-Microfluidics Chip/Triple-Quadrupole MS. In this system, transitions were acquired only during the retention window of each eluting peptide. Transitions with the highest MRM-MS intensities for the five target peptides from colon cancer biomarker candidates were automatically selected using Optimizer software. Relative to the corresponding non-dynamic system, the dynamic MRM provided significantly improved coefficients of variation in experiments with large numbers of transitions. Linear responses were obtained with concentrations ranging from fmol to pmol for five target peptides.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.86-92
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• 2011

In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip $0.18{\mu}m$. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.2
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• pp.55-59
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• 2004

Throughout manufacturing processes, pulse shaping is required for material processing and it is regarded as an important (actor according to the specific characteristics of materials. Therefore, this study suggests a highly appropriate pulse shaping technique using a multi-switching method. This is a pulse superposition method in which one flash lamp can consecutively turn on by the double switching of the discharging system. It is possible to construct a variety of pulse shapes and pulse widths by the consecutive trigger of the silicon-controlled rectifiers (SCR) of a PIC (program integrated circuit) one-chip microprocessor. The use of this technique can provide a number of advantages to people who require suitable pulse shaping for particular applications such as welding, cutting, and drilling.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.360-365
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• 2003

In this paper, we have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers on a single chip are implemented as a system-on-chip for multi-axis motion control. We also develop a PC GUI for an efficient interface control. Comparing with the commercial motion controller LM 629 it has multi-independent PID controllers so that it has several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, robot finger is controlled. The robot finger has three fingers with 2 joints each. Finger movements show that position tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.