• The Magazine of the IEIE
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• v.29 no.9
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• pp.18-30
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• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology and from them forecasts technology trends in the near future.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.458-465
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• 2013

This paper proposes a novel soft-switched auxiliary resonant circuit to provide a Zero-Voltage-Transition at turn-on for a conventional PWM boost converter in a PFC application. The proposed auxiliary circuit enables a main switch of the boost converter to turn on under a zero voltage switching condition and simultaneously achieves both soft-switched turn-on and turn-off. Moreover, for the purpose of an intelligent multi-chip power module fabrication, the proposed circuit is designed to satisfy several design constraints including space saving, low cost, and easy fabrication. As a result, the circuit is easily realized by a low rated MOSFET and a small inductor. Detail operation and the circuit waveform are theoretically explained and then simulation and experimental results are provided based on a 1.8 kW prototype PFC converter in order to verify the effectiveness of the proposed circuit.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.850-853
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• 2005

This paper presents issues of display hardware architecture, relating to memory, display driver IC architecture, and chip-to-chip interface. To achieve a low power and low cost mobile phone, not only the display architecture must be carefully selected, but also the driver-ICs optimized to accommodate the different modes of operation found in typical handheld devices. The technique of forming a photo sensor in each pixel using TFT and display module architecture are developed to add multi functions in display such as fingerprint recognition, image scanning, and integrated touch screen. Detailed architectures of IC partitioning, high-speed serial interface, D/A converter, and multi functions such as fingerprint recognition and image scanning using photo sensors are important to a power optimized system.

• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.613-624
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• 2011

An MMIC multi-function chip for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. A digital serial-to-parallel converter is included in this chip in order to reduce the number of the control interface. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a relative compact size of 24 $mm^2$(6 mm${\times}$4 mm) exhibits a transmit/receive gain of 24/15 dB and a P1dB of 21 dBm from 8.5 GHz to 10.5 GHz. The RMS errors for the 64 states of the 6-bit phase shift and attenuation were measured to $7^{\circ}$ and 0.3 dB, respectively over the frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1287-1293
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• 2008

Antenna switch module(ASM) for quad-band was developed. This module was integrated by RFIPD(RF integrated passive device) and transistor switch instead of LTCC-type device using low pass filters, diodes and passive elements in RF front end module for cellular phone. This module leads to low cost and miniaturization(The area is $5{\times}5\;mm$ and the thickness is 0.8 mm). The insertion loss and the return loss of each band were averagely measured as 1.0 dB(insertion loss), 15.1 dB(GSM/EGSM return loss) and 19 dB(DCS/PCS return loss), respectively.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.319-324
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• 2005

The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface(SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShoretStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.

• ETRI Journal
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• v.41 no.2
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• pp.262-269
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• 2019

This paper introduces a low-cost, high-performance mmWave antenna array module at 77 GHz. Conventional waveguide transitions have been replaced by 3D CPW-microstrip transitions which are much simpler to realize. They are compatible with low-cost substrate fabrication processes, allowing easy integration of ICs in 3D multi-chip modules. An antenna array is designed and implemented using multilayer coupled-fed patch antenna technology. The proposed $16{\times}16$ array antenna has a fractional bandwidth of 8.4% (6.5 GHz) and a 23.6-dBi realized gain at 77 GHz.

• Industrial Engineering and Management Systems
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• v.9 no.3
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• pp.227-241
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• 2010

A memory module industry's supply chain usually consists of multiple manufacturing sites and multiple distribution centers. In order to fulfill the variety of demands from downstream customers, production planners need not only to decide the order allocation among multiple manufacturing sites but also to consider memory module industrial characteristics and supply chain constraints, such as multiple material substitution relationships, capacity, and transportation lead time, fluctuation of component purchasing prices and available supply quantities of critical materials (e.g., DRAM, chip), based on human experience. In this research, a directed graph-based supply network planning (DGSNP) model is developed for memory module industry. In addition to multi-site order allocation, the DGSNP model explicitly considers production planning for each manufacturing site, and purchasing planning from each supplier. First, the research formulates the supply network's structure and constraints in a directed-graph form. Then, a proposed genetic algorithm (GA) solves the matrix form which is transformed from the directed-graph model. Finally, the final matrix, with a calculated maximum profit, can be transformed back to a directed-graph based supply network plan as a reference for planners. The results of the illustrative experiments show that the DGSNP model, compared to current memory module industry practices, determines a convincing supply network planning solution, as measured by total profit.