• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.34-42
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• 2012

In this paper, a wide-input range CMOS multi-mode rectifier for wireless power transfer system is presented. The output voltage of multi-mode rectifier is sensed by comparator and switches are controlled based on it. The mode of multi-mode rectifier is automatically selected by the switches among full-wave rectifier, 1-stage voltage multiplier and 2-stage voltage multiplier. In full-wave rectifier mode, the rectified output DC voltage ranges from 9 V to 19 V for a input AC voltage from 10 V to 20 V. However, the input-range of the multi-mode rectifier is more improved than that of the conventional full-wave rectifier by 5V, so the rectified output DC voltage ranges from 7.5 V to 19 V for a input AC voltage from 5 V to 20 V. The power conversion efficiency of the multi-mode rectifier is 94 % in full-wave rectifier mode. The proposed multi-mode rectifier is fabricated in a $0.35{\mu}m$ CMOS process with an active area of $2500{\mu}m{\times}1750{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.31-40
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• 2005

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• Journal of Sensor Science and Technology
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• v.4 no.4
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• pp.55-61
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• 1995

A new ISFET array chip, based on detection of the threshold voltages of ISFETs by using an adjustable input, was designed. The chip includes 240 pH-ISFETs and circuitry such as comparators, a decoder and register. The chip has increased reliability, improved accuracy, digital output capability and the possibility of multi sensor implementation. To fabricate the chip, an extended CMOS process was devised and implemented.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.147-151
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• 2024

The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Journal of IKEEE
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• v.15 no.1
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• pp.57-63
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• 2011

This paper presents a tunable band pass filter (BPF) for multi bio-signal detection. The bandwidth can be controlled by the bias current of transconductance (gm), while conventional BPF exploited switchable capacitor array for band selection. With this design technique, the die area of proposed BPF reduced to at least one tenth the area of conventional design. The simulation results show the high cut-off frequency tuning range of from 100Hz to 1Khz. The circuit was implemented with a 0.18um CMOS standard technology. Total current consumption is 1uA at the supply voltage of 1V with sub-threshold design technique.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.5 s.305
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• pp.43-50
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• 2005

This paper describes some IC(integrated circuits) design and implementation techniques of low power multi-band Gm-C bandpass filter for body composition analyzer. Proposed BPF(bandpass filter) can be selected from three bands(20 KHz, 50 KHz, 100 KHz) by control signal. To minimize die area, a simple center frequency tuning scheme is used. And to reduce power consumption, operational transconductance amplifier operated in the sub-threshold region is adopted. The proposed BPF is implemented with 0.35 um 2-poly 3-metal standard CMOS technology Chip area is $626.42um\;{\times}\;475.8um$ and power consumption is 700 nW@100 KHz.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.