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MTCMOS ASIC Design Methodology for High Performance Low Power Mobile Computing Applications  

Kim Kyosun (Department of Electronic Engineering, University of Incheon)
Won Hyo-Sig (CAE Center, Samsung Electronics)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.2, 2005 , pp. 31-40 More about this Journal
Abstract
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.
Keywords
MTCMOS; ASIC design methodology; performance enhancement; mobile computing;
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