• Journal of Power Electronics
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• v.13 no.3
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• pp.400-408
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• 2013

This paper presents a discrete state-space controller using state feedback control and feed-forward decoupling to provide a desirable control bandwidth and control stability for dynamic voltage restorers (DVR). The paper initially discusses three typical applications of a DVR. The load-side capacitor DVR topology is preferred because of its better filtering capability. The proposed DVR controller offers almost full controllability because of the multi-feedback of state variables, including one-beat delay feedback. Feed-forward decoupling is usually employed to prevent disturbances of the load current and source voltage. Directly obtaining the feed-forward paths of the load current and source voltage in the discrete domain is a complicated process. Fortunately, the full feed-forward decoupling strategy can be easily applied to the discrete state-space controller by means of continuous transformation. Simulation and experimental results from a digital signal processor-based system are included to support theoretical analysis.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.34 no.2
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• pp.76-92
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• 2023

Objectives: This study aimed to analyze research trends in autism spectrum disorder (ASD) and savant syndrome and their cognitive characteristics through a systematic literature review. The objectives of this study were to establish an overview of research trends in ASD and savant syndrome, analyze the overall characteristics of individuals with ASD and savant syndrome, and examine their cognitive characteristics. Methods: For the systematic literature review, three criteria were used to select review articles: 1) literature from peer-reviewed journals, published in the past 15 years, from 2008 to 2022; 2) subjects with ASD and savant syndrome; 3) study objectives focused on the basic phenomenon and cognitive characteristics of ASD and savant syndrome. Finally, based on the selection criteria, a total of 40 articles were included. Results: Five themes and nine subthemes were derived from the analysis of 40 studies. The five main themes were as follows: 1) What is savant syndrome? 2) Demographic characteristics of savant syndrome; 3) Spectra of savant syndrome; 4) Savant syndrome and ASD; and 5) Cognitive characteristics of ASD with savant syndrome. The subthemes of the cognitive characteristics were weak central coherence, detail-focused cognitive processing, enhanced perceptual functioning, and hyper-systemizing. Conclusion: Several studies have been conducted to understand ASD and savant syndrome; however, no single theory can specify the cognitive characteristics of people with ASD and savant syndrome. Therefore, further systematic and multi-layered research on ASD and savant syndrome are required for more comprehensive results.

• Journal of the Korean Society for Precision Engineering
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• v.10 no.4
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• pp.227-235
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• 1993

In this paper, the development of a high performance flexible controller is described. The hardware of the controller, based on VME-bus, consists of four M68020 single-board computers (32-bit) with M68881 numerical coprocessors, two M68040 single board donputers, I/O devices (such as A/D and D/A converters, paraller I/O, encoder counters), and bus-to-bus adaptor. This software, written in C and based on X-window environment with Unix operating system, includes : text editor, compiler, downloader, and plotter running in a host computer for developing control program ; device drivers, scheduler, and mathemetical routines for the real time control purpose ; message passing, file server, source level debugger virtural terminal, etc. The hardware and software are structured so that the controller might have both flexibility and extensibility. In papallel to the controller, a three degrees of freedom kinematically redundant robot has been developed at the same time. The development of the same time. The development of the robot was undertaken in order to provide, on the one hand, a computationally intensive plant to which to apply the controller, and on the other hand a research tool in the field of kinematically redundant manipulator, which is, as such, an important area. By using the controller, dynamic control of the redundant manipulator was successfully experimented, showing the effectiveness and flexibility of the controller.

• Journal of the Korean Society of Safety
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• v.12 no.4
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• pp.241-248
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• 1997

This paper presents the development procedure and application of the generic component reliability data base considering the dependency among dependent generic compendia in NPPs (Nuclear Power Plants) PSA (Probabilistic Safety Assessment) under construction or without operating history. We use MPRDP (Multi-Purpose Reliability Data Processor) code developed in KAERI (Korea Atomic Energy Research Institute) based on a PEB (Parametric Empirical Bayesian) procedure to estimate the reliability. The employed model in this study accounts for the relative credibility as well as the dependency among generic estimates. Numerical examples and the part of summarized reliability data table are provided as the application.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.12
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• pp.889-898
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• 2022

In this paper, parallel computing method on the three-dimensional electromagnetic field is proposed. The present electromagnetic scattering analysis is conducted based on the time-harmonic vector wave equation and the finite element method. The edge-based element and 2^nd -order absorbing boundary condition are used. Parallelization of the elemental numerical integration and the matrix assemblage is accomplished by allocating the partitioned finite element subdomain for each processor. The graph partitioning library, METIS, is employed for the subdomain generation. The large sparse matrix computation is conducted by MUMPS, which is the parallel computing library based on the multi-frontal method. The accuracy of the present program is validated by the comparison against the Mie-series analytical solution and the results by ANSYS HFSS. In addition, the scalability is verified by measuring the speed-up in terms of the number of processors used. The present electromagnetic scattering analysis is performed for a perfect electric conductor sphere, isotropic/anisotropic dielectric sphere, and the missile configuration. The algorithm of the present program will be applied to the finite element and tearing method, aiming for the further extended parallel computing performance.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.869-872
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• 2008

This paper presents the VHDL implementation procedure of the passive RFID tag in Ultra High Frequency RFID system. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation on prototyping board. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of the interrogation rate. Also with UART communication, verify a inventory Round in Gen2 Protocol. The verification results with the fastest data rate, 640kbps, and multi tags environment scenario show that the implemented tag spend 1.4ms transmitting the 96bits EPC to reader.

• Journal of Digital Convergence
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• v.13 no.12
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• pp.381-390
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• 2015

One of the fundamental requirements of entertainment applications is interactivity with users. The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor's computing power, memory size and available electric power of the battery. This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or octa-core. To harness the multi-core architecture, it exploits the POSIX thread, a platform-independent thread library to be able to be used in various mobile platforms such as Android, iOS, etc. As a useful application example of the methodology, a heavy matrix calculation function was transformed to a parallelized version which showed around 2.5 ~ 3 times faster than the original version in a real-world usage environment.