• 제목/요약/키워드: Multi-Chip Stacking

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Advances in Package-on-Package Technology for Logic + Memory Integration

  • Scanlan Christopher
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2005년도 ISMP
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    • pp.111-129
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    • 2005
  • Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

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Mold-Flow Simulation in 3 Die Stack Chip Scale Packaging

  • Rhee Min-Woo
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2005년도 ISMP
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    • pp.67-88
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    • 2005
  • Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • 이강욱
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.