• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.67-67
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• 2002

패키지 기술의 개발은 저비용, 고성능, 높은 패키징 효율의 추세로 가고 있다. 이러한 추세에 따라 기판재료의 개발 및 구조의 변형이 요구된다. 패키지의 한 형태인 MCM(Multi-Chip Module)에 연성기판을 사용할 경우 fine pattern이 가능하고 부피가 작기 때문에 패키지의 효율이 좋고 또한 reel to reel process에 적용이 가능하기 때문에 대량생산의 이점을 가지고 있다. 연성기판은 좋은 전기적 특성을 가진 polyimide와 구리 층으로 구성된다. 그러나 polyimide와 구리 계층 사이에 약한 접착력과 구리로의 polyamic acid의 diffusion, 다층 기판의 제조의 어려움 등의 문제점을 남겨두고 있다. 본 연구는 일반적인 polyimide/copper가 구조가 가지고 있는 문제점을 해결하고 구리 패턴을 제작하기 위해 에칭을 쓰는 것을 배제함으로 fine pattern을 이루어 내었으며 전기도금으로 완전하게 채워진 pluged via을 사용함으로 각층간의 연결에 신뢰성을 부여하였다. 또한, 연성기판의 구조적인 문제점인 해결하여 다층 연성기판을 제조하려고 한다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.47-53
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• 2002

In this study, two different (NiCuZn)-ferrite which were fabricated by using ultra-fine powders synthesized by the wet processing and conventionally commercialized powder, were investigated and compared each other in terms of the low temperature sintering and electromagnetic properties. Composition of x and w in $(Ni_{0.4-x}Cu_xZn_{0.6})_{1+w}(Fe_2O_4)_{1-w}$ were controlled as 0.2 and 0.03, respectively. The sintering temperature were $900^{\circ}C$ for ultra-fine powders by way of initial heat treatment and $1150^{\circ}C$ for commercialized powders. The (NiCuZn)-ferrite by ultra-fine powders showed love. sintering temperature than that of commercialized powders by over $200^{\circ}C$, and excellent electromagnetic properties such as the quality factor which is a important factor in the multi-layered chip inductor. In addition, characteristics of B-H hysteresis, crystallinity, microstructure and powder morphology were analyzed by a vibrating sample method(VSM), x-ray diffractometer(XRD), transmission electron microscope (TEM) and scanning electron microscope(SEM).

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.31-36
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• 2015

The demand for multi-functionality, high density, high performance, and miniaturization of IC devices has caused the technology paradigm shift for electronic packaging. So, thermal management of new packaged chips becomes a bottleneck for the performance of next generation devices. Among various thermal solutions such as heat sink, heat spreader, TIM, thermoelectric cooler, etc. on-chip liquid cooling module was investigated in this study. Micro-channel was fabricated on Si wafer using a deep reactive ion etching, and 3 different micro-channel designs (straight MC, serpentine MC, zigzag MC) were formed to evalute the effectiveness of liquid cooling. At the heating temperature of $200^{\circ}C$ and coolant flow rate of 150ml/min, straight MC showed the high temperature differential of ${\sim}44^{\circ}C$ after liquid cooling. The shape of liquid flowing through micro-channel was observed by fluorescence microscope, and the temperarue differential of liquid cooling module was measuremd by IR microscope.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.11-15
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• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1097-1098
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.687-688
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• 2009

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.