• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of Internet Computing and Services
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• v.11 no.2
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• pp.49-60
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• 2010

H.264/AVC offers a better encoding efficiency than conventional video standards by adopting many new encoding techniques. However, the advanced coding techniques also add to the overall complexity for H.264/AVC encoder. Accordingly, it is necessary to perform optimization to alleviate the level of complexity for the video encoder. The amount of computation for motion estimation is of particular importance. In this paper, we propose a diamond web-grid search algorithm combined with efficient stationary block skip method which employs full diamond and dodecagon search patterns, and the variable thresholds are used for performing an effective skip of stationary blocks. The experimental results indicate that the proposed technique reduces the computations of the unsymmetrical-cross multi-hexagon-grid search algorithm by up to 12% while maintaining a similar PSNR performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.75-87
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• 2009

We propose in this paper a novel approach to image fusion in which the fusion rule is guided by optimizing an image clarity function. A Genetic Algorithm is used to stochastically select, comparative to the clarity function, the optimum block from among the source images. A novel nested Genetic Algorithm with gifted individuals found through bombardment of genes by the mutation operator is designed and implemented. Convergence of the algorithm is analytically and empirically examined and statistically compared (MANOVA) with the canonical GA using 3 test functions commonly used in the GA literature. The resulting GA is invariant to parameters and population size, and a minimal size of 20 individuals is found to be sufficient in the tests. In the fusion application, each individual in the population is a finite sequence of discrete values that represent input blocks. Performance of the proposed technique applied to image fusion experiments, is characterized in terms of Mutual Information (MI) as the output quality measure. The method is tested with C=2 input images. The results of the proposed scheme indicate a practical and attractive alternative to current multi-focus image fusion techniques.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.927-934
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• 2003

Database query optimates the selectivety of a query to find the most efficient access plan. Multi-dimensional selectivity estimation technique is required for a query with multiple attributes because the attributes are not independent each other. Histogram is practically used in most commercial database products because it approximates data distributions with small overhead and small error rates. However, histogram is inadequate for a query with multiple attributes because it incurs high storage overhead and high error rates. In this paper, we propose a novel method for multi-dimentional selectivity estimation. Compressed information from a large number of small-sized histogram buckets is maintained using the discrete cosine transform. This enables low error rates and low storage overheads even in high dimensions. Extensive experimental results show adventages of the proposed approach.

• Polymer(Korea)
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• v.37 no.4
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• pp.470-477
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• 2013

Multi-walled carbon nanotube (MWCNT) based nano-composite pastes having a high filler content are prepared for the facile fabrication of a counter electrode (CE) of dye-sensitized solar cell (DSSC). A polystyrene-based functional block copolymer is prepared through a controlled "living" radical polymerization technique, affording a surface modifier for the dispersion control of MWCNT in the paste. Physical dispersion through a ball-milling method additionally confirms the importance of the dispersion control, providing DSSC with enhanced processibility and improved solar-to-electricity energy conversion efficiency (${\eta}$) values. The performances of the DSSCs are further improved through the incorporation of minor amount of platinum (Pt) nanoparticles into the MWCNT pastes. The DSSC with the Pt/MWCNT hybrid CE exhibits very high ${\eta}$ values, which is superior to that of DSSC with the standard Pt CE.

• Radiation Oncology Journal
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• v.9 no.2
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• pp.343-350
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• 1991

The quasi-conformation therapy was performed to get a homogeneous dose distributions for irregeular shaped tumor lesion by using the arc moving beam and beam modifying filter which was made by cerrobend alloy($\rho$=9.4 g/cc) metal. In our dose calcuation programme, it was fundmentally based on Clarkson's method to calcuate the irregular multi-step block field in rotation therapy. In this study, the expected relative depth doses under multipartial attenuator agree well with measured data at same plane. The results of comparison the dose computation with that of TLD measurement are very closed within ${\pm}5\%$ uncertainties in the irradiation to phantom with quasi-comformation method. And it has shown that irregular typed multi-step filter can be applied to quasi-conformation therapy in high energy radiation plannings.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.148-156
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• 2013

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through independently operating in each dedicated time periods. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple was 11 mV at 3.3V output voltage. Over/undershoot voltage was 10mV/19.6mV at 3.3V output voltage. The noise performance was simulated at 800mA and 100KHz load regulation. Core circuit can be implemented small size in $700{\mu}m{\times}800{\mu}m$ area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD $0.35{\mu}m$ technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1433-1443
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• 2004

The power line modem proposed in this paper transmits the remote control signal using CSK(Code Shift Keying) and DS/SS method. The CSK technique provides the increased capacity of transmission and robustness towards noise. Besides, the DS/SS technique provides protection against narrow-band Gaussian interference and multi-path interference. The modem supports full-duplex communication using FDD(Frequency Division Duplex) and the modem structure for forward link is same with that for reverse link. To switch each sub-controlled unit smoothly, 4/$\pi$-DQPSK is adopted for noncoherent demodulation. The PN code for spreading spectrum seues to divide each group which consists of sub-controlled units and Walsh code is used for the M-ary CSK technique. Each block is designed and verified with TMS320C5402 DSP. We show the superiority of the proposed method by analyzing numerically the system performance for the factors of the DS/SS and CSK method ullder additive white Gaussian noise and PBI.