• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 반도체디스플레이기술학회지
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• 제6권1호
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• pp.17-22
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• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.837-838
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• 2013

• 한국정밀공학회지
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• 제20권10호
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• 전기학회논문지
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• 제57권4호
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• pp.653-659
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• 2008

This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

• 마이크로전자및패키징학회지
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• 제9권1호
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• pp.43-48
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• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• 한국산학기술학회논문지
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• 제12권3호
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• pp.1479-1487
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• 2011

모바일 IT기기 등의 전자부품 분야에서 다기능, 고용량 메모리를 가능하게 하는 패키지의 중요성이 점차 증대되고 있다. 이러한 목적으로 여러개의 칩을 하나의 패키지에 실장하여 다기능, 고용량을 구현하는 Multi Chip Package(MCP)가 활용되고 있다. 이러한 MCP에서 칩과 칩간 접합 혹은 칩과 지지부재(substrate)간 접합을 구현하기위해 에폭시계 필름형 접착제가 사용되고 있다. 에폭시, 아민, 머캡탄, 아이소시아네이트 등의 유기 반응기를 가진 실란커플링제를 적용하여 에폭시계 필름형 접착제에 대한 점착성과 신뢰성을 확인하였다. 결과로부터 에폭시계 반응기를 가진 실란커플링제를 적용한 시료의 점착성과 필특성이 가장 뛰어났으며, 내습 테스트에서 계면파괴가 억제되어 가장 좋은 신뢰성을 나타내었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.485-486
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• 2012

• 한국에너지공학회:학술대회논문집
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• 한국에너지공학회 2004년도 추계 학술발표회 논문집
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• pp.257-262
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• 2004

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2011년 춘계학술대회논문집
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.