• 제목/요약/키워드: Module design

검색결과 4,007건 처리시간 0.033초

Hardware design and control method for controlling an input clock frequency in the application

  • Lee, Kwanho;Lee, Jooyoung
    • International Journal of Advanced Culture Technology
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    • 제4권4호
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    • pp.30-37
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    • 2016
  • In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

능동위상배열안테나용 수신 빔 성형모듈 설계 (The Design of Beam Forming Module for Active Phased Array Antenna System)

  • 정영배;엄순영;전순익;채종석
    • 한국전자파학회:학술대회논문집
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    • 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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    • pp.118-122
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    • 2002
  • This paper is concerned with the design of the beam forming module that is a key unit of the active phased array antenna(APAA) system for mobile satellite communications. This module includes two blocks for main signal and tracking signal. Main signal block has the role of transmitting input signal from phased away antenna to tracking signal block. And, tracking signal block executes main roles, beam forming of tracking signal and electronic beam control. The several electrical performances of this module, phase characteristics and linear gain, etc., agreed with specifications needed for APAA, and for more clear verification of the performances, the satellite communication test of the APAA including the modules was accomplished in the outdoors.

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중소형 수문 설계 시스템 개발 (Development of the Design System for a Small and Medium Watergate)

  • 김인주;김일수;박창언;성백섭;송창재
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2001년도 춘계학술대회 논문집
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    • pp.535-539
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    • 2001
  • The aim of this paper presents to develop a computer-aided design system for water gate on AutoCAD R2000system. The developed system has been written in AutoCAD and Visua ILISP with a personal computer, and is composed four modules which are the gate-lifter input module, guide-frame input module, template input module and upgrade module. Based on knowledge-based rules, the system is designed by considering several factors, such as width and height of a water gate, material, object of product and maximum depth of water. Employing the developed system enable the designer and manufactures of water gate to be more efficient in this field, and its potential capability for enhancement included FEM(Finite Element Method) and quotation system.

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B-ISDN용 ATM AAL 계층의 IP 설계 (IP Design of ATM AAL Module for B-ISDN)

  • 손승일;김형준
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.261-264
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    • 2001
  • In this paper, we design IP of ATM AAL layer for B-ISDN. The designed ATM AAL module supports the function for AAL type 0, AAL type 3/4, AAL type 5. The designed IP provides for automatic CRC-32 and CRC-10 for AAL type and AAL type 3/4. Also our IP inserts and extracts the header and trailer for each type automatically. After HDL description, it is verified by the simulation. The designed U is implemented in Xilinx FPGA. Rx AAL module operates at 35MHz and Rx AAL module operates at 50MHz. The designed IP can be applicable in high-speed ATM SAR(Segmentation and Reassembly) chip.

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주파수 호핑방식 무선 LAN을 위한 PLCP 부계층 프로토콜 기능 구현 연구 (A Study on the implementation of PLCP sublayer for Frequency Hopping Wireless LAN)

  • 이선희;기장근
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.837-840
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    • 1999
  • In this paper, we design and verify the hardware circuit that performs PLCP(Physical Layer Convergence Protocol) protocol functions of physical layer in IEEE 802.11 frequency hopping WLAN(Wireless Local Area Network). Altera MAX+PLUS I $I^{〔1〕}$ is used as a design tool. The designed circuit consists of control register module to interface with upper layer, FIFO module to transmit/receive data with upper layer, TX function module, and RX function module. It is verified that the developed circuit conforms well to the IEEE 802.11 standard specification and can support both 1Mbps and 2 Mbps transmission rate by simulation. The developed circuits can be utilized for the implementation of protocol processor in wireless LAN areas.

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GIS기반을 이응한 도심지 터널굴착에 따른 인접 구조물 손상평가 시스템 개발 (Development of GIS Based Risk Assessment System for Adjacent Structures Due to Tunnelling-Induced Ground Movements in Urban)

  • 윤효석;박용원;오영석;김제규
    • 한국지반공학회:학술대회논문집
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    • 한국지반공학회 2001년도 봄 학술발표회 논문집
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    • pp.493-500
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    • 2001
  • The construction of bored tunnels in soft ground inevitably causes ground movements. In the urban environment these may be of particular significance, because of their influence on buildings, other tunnels and services. The prediction of ground movements and the assessment of the potential effects on the structures is therefore an essential aspect of planning, design and construction of a tunnelling project in the urban environment. In this study, to minimize the effect of tunnelling-Induced ground movements on the adjacent structures, a system for tile settlement risk management was developed. The GIS based risk assessment system for adjacent structures developed in this study consists of several modules such as building information module, settlement evaluation module, potential risk assessment module for adjacent structures, and analysis module for monitoring data. This system focuses on controlling and managing construction processes that may lead to settlement In the surrounding buildings and can contribute to producing the optimum technical and economic design.

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FPGA를 이용한 AC 전동기의 벡터 제어 모듈 설계 (Design of Vector Control Module for AC Motor Using FPGA)

  • 김석환;임정규;서은경;신휘범;이현우;정세교
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2005년도 전력전자학술대회 논문집
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    • pp.254-256
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    • 2005
  • This paper describes a design of a vector control module for AC motor using high density FPGA. In the proposed vector controller, the vector control blocks including inverse dq transform, space vector PWM and quadrature encoder pulse module are implemented in a FPGA using a VHDL. The simulation results are provided to show the validity of the proposed vector control module.

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2중 경사형 A/D 컨버터의 하이브리드 모듈화 설계와 성능 개선 (Design and Improvement of a hybrid module for Dual Slope A/D converter)

  • 박찬원;이종호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 G
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    • pp.3230-3232
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    • 1999
  • In this paper describes the design and improvement of a hybrid module for dual slope A/D converter. Since the input voltage to be converted is very sensitive and small. A/D converter must have the temperature stability. low-drift, and the high-resolution the conversion. A dual slop A/D converter circuit which is controlled by microprocessoer has been developed to reduce the offset voltage and the drift characteristics of operation amplifiers, and to improve the A/D conversion speed. Also hybrid module has been adapted to obtain the to obtain the stable and accurate A/D conversion for low cost use. The evaluation of the designed hybrid module has been shown as having a good performance, which will give usefull application to the industrial measurements use.

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자동차 현가모듈의 내구설계를 위한 가상 내구시험기법 정립 및 응용 (Virtual Durability Test Procedures and Applications on Design of a Vehicle Suspension Module)

  • 손성효;허승진
    • 한국자동차공학회논문집
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    • 제11권4호
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    • pp.144-150
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    • 2003
  • Recently, the virtual test techniques using computer simulation play an important part in the vehicle development procedures in order to reduce the development time and cost by replacing the physical prototypes of the vehicle components or systems with the virtual prototypes. In this paper, virtual durability test procedures for the vehicle suspension module have been developed. Virtual durability test consists of dynamic simulation computing load history of suspension components, fatigue analysis computing the life of components. A vehicle suspension module for dynamic simulation are developed and validated by comparison with the measured data obtained from the field vehicle test. And on the basis of the validated vehicle suspension model, fatigue analysis has been performed for the virtual durability design of the suspension components.

Efficient Implementation of the MQTT Protocol for Embedded Systems

  • Deschambault, Olivier;Gherbi, Abdelouahed;Legare, Christian
    • Journal of Information Processing Systems
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    • 제13권1호
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    • pp.26-39
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    • 2017
  • The need for embedded devices to be able to exchange information with each other and with data centers is essential for the advent of the Internet of Things (IoT). Several existing communication protocols are designed for small devices including the message-queue telemetry transport (MQTT) protocol or the constrained application protocol (CoAP). However, most of the existing implementations are convenient for computers or smart phones but do not consider the strict constraints and limitations with regard resource usage, portability and configuration. In this paper, we report on an industrial research and development project which focuses on the design, implementation, testing and deployment of a MQTT module. The goal of this project is to develop this module for platforms having minimal RAM, flash code memory and processing power. This software module should be fully compliant with the MQTT protocol specification, portable, and inter-operable with other software stacks. In this paper, we present our approach based on abstraction layers to the design of the MQTT module and we discuss the compliance of the implementation with the requirements set including the MISRA static analysis requirements.