• ETRI Journal
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• v.33 no.6
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.25-31
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• 2021

This paper describes the design of a power cell-based pulsed power modulator with fast rise times. The pulse-generating section of the pulse power modulator is a series stack of power cells. Each power cell is composed of a storage capacitor, a pulse switch, and a bypass diode. When the pulse switches are turned on, the capacitors are connected in series and the sum of voltages is applied to the load. For output pulses with fast rise times, an IGBT with fast turn-on characteristics is adopted as a pulse switch and the optimized gate driving method is used. Pspice simulation is performed to account for the gate driving method. A 10 kV, 12-power cell-based pulsed power modulator is tested under resistive load and plasma reactor load. The rise times of output pulses less than 20 ns are confirmed, showing that the pulsed power modulator can be effectively applied to pulsed power applications with fast rise times.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.475-483
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• 2012

This paper presents new type of the hybrid supply modulator for the next reconfigurable transmitters. The efficiency of the hybrid supply modulator is one of the most important performance. For enhancement the efficiency, multi-switching structure in the hybrid supply modulator is employed. Additionally, input envelope signal sensing stage is employed for implementation multi-mode operation. To compare the performance of the proposed hybrid supply modulator, the conventional hybrid supply modulator is also designed. The measured efficiency of the proposed hybrid supply modulator is 85 %/84 %/79 % for EDGE/WCDMA/LTE signals which have 384 kHz/3.84 MHz/5 MHz bandwidth, respectively. The efficiency of the proposed hybrid supply modulator is higher than the conventional hybrid supply modulator. Therefore, this structure shows good candidate for the reconfigurable transmitters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.6
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• pp.44-49
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• 1974

reactance modulator composed of multi-stage phase modulator utilizing VVC diodes as variable reactance elements and an oscillartor-modulator, utilizing a VVC diode as a tuning element, coupled to a crystal resonator through an artificial λ/4 network are introduced and their characteristics as FM modulator are compared mutually from the practical view points. especially, to get high modulation sensitivity of reactance modulators using VVC diodes, making a multi-stage modulation distortion characteristics of multi-stage modulator was necessary. The harmonic moj\dulationdistorion characteristics of multi-stage reactance modulator is analized in detall. Multi-stage reachance modulator is preferable to maintain sufficiently stable carrier frequency over the wide range of temperature and a mobile-transceiver was made through this method. On the other hand, FM-Quartz oscillator using a VVc diode is suitavle for handy-talkies of good quality were made through this method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1310-1318
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• 1998

Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of the korean Society of Automotive Engineers
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• v.24 no.6
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• pp.17-21
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• 2002

• Proceedings of the Optical Society of Korea Conference
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• 1996.09a
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• pp.32-32
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• 1996

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.235-245
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• 2014

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.847-851
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• 2011

In this paper, a novel IQ modulator that precisely controls the magnitude and phase of input signals is proposed. The proposed IQ modulator consists of low phase deviation attenuators, a splitter, and a combiner. In order to overcome the phase deviation characteristics found in conventional attenuators, a novel phase compensation technique has been adopted and mathematically analyzed. Linear vector arrays along the center point with large magnitude output signal variations in a full $360^{\circ}$ phase control are achieved on a polar plane by the proposed IQ modulator.