• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.425-437
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• 2017

For efficient hardware (HW) implementation of elliptic curve cryptography (ECC), various sub-modules for the underlying finite field operations should be implemented efficiently. Among these sub-modules, modular inversion (MI) requires the most computation; therefore, its performance might be a dominant factor of the overall performance of an ECC module. To determine the most efficient MI algorithm for an HW ECC module, we implement various classes of MI algorithms and analyze their performance. In contrast to the common belief in previous research, our results show that the right-shift binary inversion (RS) algorithm performs well when implemented in hardware. In addition, we present optimization methods to reduce the area overhead and improve the speed of the RS algorithm. By applying these methods, we propose a new RS-variant that is both fast and compact. The proposed MI module is more than twice as fast as the other two classes of MI: shifting Euclidean (SE) and left-shift binary inversion (LS) algorithms. It consumes only 15% more area and even 5% less area than SE and LS, respectively. Finally, we show that how our new method can be applied to optimize an HW ECC module.

• International Journal of Contents
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• v.3 no.2
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• pp.40-43
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• 2007

This paper proposed a new modular inverse algorithm based on the right-shifting binary Euclidean algorithm. For an n-bit numbers, the number of operations for the proposed algorithm is reduced about 61.3% less than the classical binary extended Euclidean algorithm. The proposed algorithm implementation shows substantial reduction in computation time over Galois field GF(p).

• Journal of Korea Multimedia Society
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• v.20 no.2
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• pp.289-297
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• 2017

When implementing a hardware elliptic curve cryptosystem (ECC) module, the efficient design of Modular Inverse (MI) algorithm is especially important since it requires much more computation than other finite field operations in ECC. Among the MI algorithms, binary Right-Shift modular inverse (RS) algorithm has good performance when implemented in hardware, but Montgomery Modular Inverse (MMI) algorithm is not considered in [1, 2]. Since MMI has a similar structure to that of RS, we show that the area-improvement idea that is applied to RS is applicable to MMI, and that we can improve the speed of MMI. We designed area- and speed-improved MMI variants as hardware modules and analyzed their performance.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of Korea Multimedia Society
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• v.6 no.4
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• pp.610-619
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• 2003

This paper presents a concept of cellular automata and a modular exponentiation algorithm and implementation of a basic EIGamal encryption by using cellular automata. Nowadays most of modular exponentiation algorithms are implemented by a linear feedback shift register(LFSR), but its structure has disadvantage which is difficult to implement an operation scheme when the basis is changed frequently The proposed algorithm based on a cellular automata in this paper can overcome this shortcomings, and can be effectively applied to the modular exponentiation algorithm by using the characteristic of the parallelism and flexibility of cellular automata. We also propose a new fast multiplier algorithm using the normal basis representation. A new multiplier algorithm based on normal basis is quite fast than the conventional algorithms using standard basis. This application is also applicable to construct operational structures such as multiplication, exponentiation and inversion algorithm for EIGamal cryptosystem.

• ETRI Journal
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• v.41 no.6
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.2
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• pp.79-84
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• 2012

Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.190-194
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• 2002

Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.1
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• pp.9-17
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• 1970

The paper presents pole optimization in RC network of active RC filter using current inversion negative impedance converter. And also empais is placed on improving the stability of the active RC filter. Experimental results obtained with active RC low pass filter, having Chebyshev 2nd order response and modular angle 55$^{\circ}$, cutoff frequency 3.4KC, are shown and compared with theoretical curves.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1095-1102
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• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.