• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.1
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• pp.38-47
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• 2014

This paper describes the application of discrete event systems theory to the design of an automated laboratory system. Current automated laboratory systems typically consist of several interacting processes that must be carefully sequenced to avoid any possible process conflicts. Discrete Event Systems (DES) theory and Supervisory Control Theory (SCT) can be applied together as effective methods of modeling the system dynamics and designing supervisory controllers to precisely sequence the many processes that such systems might involve. Classical approaches to supervisory controller design tend to result in complex controller structures that are difficult to implement, maintain, and upgrade. In this paper, a new approach to designing supervisory controllers for automated laboratory systems is introduced. This new approach uses a modular controller structure that is easier to implement, maintain, and upgrade, and deals with "state explosion" issues in a novel and efficient way.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.37-43
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• 2010

In this paper, we implement that hollow type joint using two more than general motor and design for compact structure embedded electronic parts in the development of 7 degree of freedom manipulator. We propose a method to overcome risk and the limit of operating radius which are point out as a limit of previous industrial robot. and also propose to more efficient and stable manipulator implement method.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.19 no.6
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• pp.875-882
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• 2010

Nowadays, the global market requires a variety of products and shorter life cycle to fulfill the diverse demands of customers. To survive in the turbulent and competitive markets, automobile assembly companies must design and implement manufacturing systems that respond rapidly to market demands. In this paper, methods for reconfiguring system based on modular concept is proposed using AR(Augmented reality) technologies. First, the relationship matrixes between change drivers and system components are generated to divide existing manufacturing system to each module. And, new change drivers are selected based on required function in new system. Through the modification of relationship matrix, the concept design of new system is proposed and implemented in AR environment. Finally, according to proposed methods and procedure in this paper, the existing cockpit assembly system is reconfigured to spare tire assembly system as a case study. As the use of the modular-based reconfiguration method in AR environment, the time and cost for reconfiguring manufacturing system will be reduced dramatically.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.437-444
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• 2014

The integrated modular avionics (IMA) system has quite a number of line repalceable moduels (LRMs) in a cabinet. The LRM performs functions like line replaceable units (LRUs) in federated architecture. The video processing module (VPM) acts as a video bus bridge and gateway of ARINC 818 avionics digital video bus (ADVB). The VPM is a LRM in IMA core system. The ARINC 818 video interface and protocol standard was developed for high-bandwidth, low-latency and uncompressed digital video transmission. FPGAs of the VPM include video processing function such as ARINC 818 to DVI, DVI to ARINC 818 convertor, video decoder and overlay. In this paper we explain how to implement VPM's Hardware. Also we show the verification results about VPM functions and IP core performance.

• Journal of KIISE:Software and Applications
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• v.37 no.10
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• pp.736-744
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• 2010

Log data collected from mobile devices contain diverse and meaningful personal information. However, it is not easy to implement a context-aware mobile agent using this personal information due to the inherent limitation in mobile platform such as memory capacity, computation power and its difficulty of analysis of the data. We propose a method of selective inference for modular Bayesian Network for context-aware mobile agent with effectiveness and reliability. Each BN module performs inference only when it can change the result by comparing to the history module which contains evidences and posterior probability, and gets results effectively using a method of influence score of the modules. We adopt memory decay theory and virtual linking method for the evaluation of the reliability and conservation of casual relationship between BN modules, respectively. Finally, we confirm the usefulness of the proposed method by several experiments on mobile phones.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.157-162
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• 2010

Due to the IT development, RFID/USN became very familiar means of communication. However, because of increased number, security, and size constraints of nodes, it is insufficient to implement a variety of services. To solve these problems, this paper suggests RI-RSA, which is an appropriate asymmetric cryptographic system for RFID/USN environment. The proposed RI-RSA cryptographic system is easy to implement. To increase the processing speed, RI-RSA was suggested by subdividing the multiplication section into two-dimensional, where bottleneck phenomena occurs, and it was implemented in the hardware chip level. The simulation result verified that it caused 6% of circuit reduction, and for the processing speed, RI-RSA was 30% faster compare to the existing RSA.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.47-50
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• 2004

In this paper, we implement an Elliptic Curve Cryptosystem(ECC) processor for DTCP. Because DTCP(Digital Transmission Content Protection) uses GF(p), where p is a 160-bit prime integer, we design a scalar multiplier based on GF(p). The scalar multiplier consists of a modular multiplier and an adder. The multiplier uses montgomery algorithm which is implemented with CSA(Carry-save Adder) and CLA(Carry-lookahead Adder). Our new scalar multiplier has been synthesized using Samsung 0.18 um CMOS technology and the maximum operation frequency is estimated 98 MHz, with the size about 65,000 gates. The resulting performance is 29.6 kbps, that is, it takes 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.293-297
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• 1993

In this paper, a new design method for Assembly Line Control System(ALCS) is presented. This system consists of five independent modules having their own specific functions such as production management, facility management material management, quality management, and remote control. To implement the ALCS, we propose design of the common data management module(CDMM). This module has the roles of integrating the above five modules and of communicating the common data between them. Using this method, we realize an information management method in the view of CIM. In addition, we standardize the inter-communication of common data between machines having different interface protocols.