• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Korean Institute of Interior Design Journal
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• v.22 no.4
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• pp.3-14
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• 2013

This study is aimed to specify the meaning of the body and the design trends in contemporary architecture. Architecture is based on the human life of various meaning, events, experiences, images, senses and interactions through the body. Thoughts, behaviors, and senses of human are interrelated in architectural experiences. Individuals experience the built environments and space, not through the ideas but through the senses and movements of the body. So, bodies make the real space of architecture. Contemporary architecture accepts the theory of phenomenology and places on the thoughts of Maurice Merleau-Ponty, Heidegger, Nroberg Schulz and so on. Such researches effect on the architectural trends to make design processes works on the programs in views of the expansion and the structuralization of human body. In detail, the aim of this study is to analyse the architecture as the fields of the subject with body as the center, design processes and principles changed form metaphysical thought to phenomenological discourse, and the design trends in contemporary architecture at last. In process of movements, vision centered architecture moves into the bodily experienced architecture and changed the trends from absolute form design to design of relative processes. In conclusion, architectural formation-dissolution-reconstitution of body creates the architectural thoughts such as human proportions, perspective space, ergonomics, modular, organic architecture, experience space, synesthesia, event architecture, fashion-invoked architecture, interactive surfaces, metamorphosis, and others.

• Journal of Aerospace System Engineering
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• v.8 no.2
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• pp.21-26
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• 2014

The aircraft manufacturers are constantly driving to reduce manufacturing lead times and cost at the same time as the product complexity increases and technology continues to change. Integrated Modular Avionics (IMA) is a solution that allows the aviation industry to manage their avionics complexity. IMA defines an integrated system architecture that preserves the fault containment and 'separation of concerns' properties of the federated architectures. In software side, the air transport industry has developed ARINC 653 specification as a standardized Real Time Operating System (RTOS) interface definition for IMA. It allows hosting multiple applications of different software levels on the same hardware in the context of IMA architecture. This paper describes a study that provided the avionics software design for separation of fault and backup of core function to reduce workload of pilot with cost efficiency.

• Journal of IKEEE
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• v.19 no.3
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• pp.357-365
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• 2015

Recently, embedded systems such as aircraft and automobilie, are developed as modular architecture instead of federated architecture because of SWaP(Size, Weight and Power) issues. In addition, partition operating system that support multiple logical node based on partition concept were recently appeared. Distributed recovery block is fault tolerance design scheme that applicable to mission critical real-time system to support real-time take over via real-time synchronization between participated nodes. Because of real-time synchronization, single-core based computer is not suitable for partition based distributed recovery block design scheme. Multi-core and AMP(Asymmetric Multi-Processing) based partition architecture is required to apply distributed recovery block design scheme. In this paper, we proposed design scheme of distributed recovery block on the multi-core based supervised-AMP architecture partition operating system. This paper implements flight control simulator for avionics to check feasibility of our design scheme.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.57-64
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• 2019

Recently, avionics systems are being developed as integrated modular architecture applying the modular integration design of the functional unit to reduce maintenance costs and increase operating performance. Additionally, a partitioning operating system based on virtualization technology was used to process various mission control functions. In virtualization technology, the CPU processing load distribution is a key consideration. Especially, the uncertainty of the I/O processing time is a risk factor in the design of reliable avionics systems. In this paper, we examine the influence of the I/O processing method by comparing and analyzing the CPU processing load by the I/O processing method through use of case analysis and applying it to the example of spatial-temporal partitioning.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2755-2757
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• 2002

In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.2
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• pp.79-84
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• 2012

Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• Journal of the Korean housing association
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• v.21 no.6
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• pp.43-52
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• 2010

It has applied the design method of face to face dimension, an MC (Modular Coordination) design method, at design steps of an apartment house for standardization of architecture. But It has been still using center line size. A construction limit isn't specific on these center line size, and dead space occurs with excessive gaps as size matching isn't performed well between structural sieve and parts. And above all, measurement before construction isn't to expect standardization, and to increase custom-made furniture. We investigate manufacture of a preferential domestic system kitchen and construction state, and we derive from a problem in viewpoints of standardization for this. And we utilized a reference plane, and we present construction document and design plan in order to solve these problems. And we analyze an effect got by application of the assembly basis aspect that we presented, and we can raise efficiency of standardization of housing and construction industry, and we light ultimately up.

• 제어로봇시스템학회:학술대회논문집
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• 1994.10a
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• pp.638-642
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• 1994

The objectives of this work are to present the dynamic simulation strategy based on cluster-modular approach and to develop a prototype simulator. In addition, methods for the improvement of computational efficiency and applicability are studied. A process can be decomposed into several clusters which consist of strongly coupled units depending upon the process dynamics or topology. The combined approach of simultaneous and sequential simulation based on the cluster structure is implemented within the developed dynamic process simulator, MOSA(Multi Objective Simulation Architecture). Dynamic simulation for a utility plant is presented as a case study in order to prove the efficiency and flexibility of MOSA.